View AC82GL40-SLB95_6371965.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

intel? celeron? mobile processor dual-core on 45-nm process datasheet for platforms based on mobile inte l? 4 series express chipset family september 2009 document number: 321111-003
2 datasheet legal lines and disclaimers information in this document is provided in connection with inte l? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products in cluding liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. unless otherwise agreed in writing by intel, the intel products are not designed nor intended for any application in which the failure of the intel product could create a situation where personal injury or death may occur. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the a bsence or characteristics of any features or instructions marked ?reserved? or ?undefined.? intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the information here is subject to change without notice. d o not finalize a design with this information. the products described in this document may contain design defects or errors known as errata which may cause the product to dev iate from published specifications. current characterized errata are available on request. contact your local intel sales office or yo ur distributor to obtain the latest specifications and before placing your product o rder. enabling execute disable bit functionality requires a pc with a processor with execute disable bit capability and a supporting operating system. check with your pc manufacturer on whether your system delivers execute disable bit functionality. enhanced intel speedstep? technology for specified units of this processor is available. see the processor spec finder at http: // processorfinder.intel.com or contact your intel representative for more information. intel? virtualization technology requires a computer system with an enabled intel? processor, bios, virtual machine monitor (vm m) and, for some uses, certain platform software enabled for it. functionality, performance or other benefits will vary depending on hardware an d software configurations and may require a bios update. software applications may not be co mpatible with all operating systems. please check with your a pplication vendor. this device is protected by u.s. patent numbers 5,315,448 and 6,516,132, and other intellectual property rights. the use of mac rovision's copy protection technology in the device must be authorized by macr ovision and is intended for home and other limited pay-per-view u ses only, unless otherwise authorized in writing by macrovision. reverse engineering or disassembly is prohibited. 64-bit computing on intel architecture requires a computer system with a processor, chipset, bios, operating system, device dri vers and applications enabled for intel? 64 architecture. processors will not operate (including 32-bit operation) without an intel? 64 architecture- enabled bios. performance will vary depending on your hardware and software configurations. consult with your system vendor for more informat ion. intel, pentium, intel core, intel core 2, intel speedstep and the intel logo are trademarks of intel corporation in the u.s. an d other countries. *other names and brands may be cl aimed as the property of others. copyright ? 2008, intel corporation. all rights reserved.
datasheet 3 contents 1introduction .............................................................................................................. 7 1.1 terminology ....................................................................................................... 8 1.2 references ......................................................................................................... 9 2 low power features ................................................................................................ 11 2.1 clock control and low power states .................................................................... 11 2.1.1 core low-power states ........................................................................... 12 2.1.2 package low-power states ...................................................................... 13 2.2 low-power fsb features .................................................................................... 15 2.3 processor power status indicator (psi#) signal..................................................... 15 3 electrical specifications ........................................................................................... 17 3.1 power and ground pins ...................................................................................... 17 3.2 fsb clock (bclk[1:0]) and processor clocking ...................................................... 17 3.3 voltage identification ......................................................................................... 17 3.4 catastrophic thermal protection .......................................................................... 20 3.5 reserved and unused pins.................................................................................. 20 3.6 fsb frequency select signals (bsel[2:0])............................................................ 21 3.7 fsb signal groups............................................................................................. 21 3.8 cmos signals ................................................................................................... 23 3.9 maximum ratings.............................................................................................. 23 3.10 processor dc specifications ................................................................................ 24 4 package mechanical specific ations and pin information .......................................... 29 4.1 package mechanical specifications ................ ....................................................... 29 4.2 processor pinout and pin list .............................................................................. 33 4.3 alphabetical signals reference ............................................................................ 53 5 thermal specifications and design considerations .................................................. 61 5.1 monitoring die temperature ............................................................................... 61 5.1.1 thermal diode ....................................................................................... 62 5.1.2 thermal diode offset .............................................................................. 64 5.1.3 intel? thermal monitor........................................................................... 65 5.1.4 digital thermal sensor............................................................................ 66 5.1.5 out of specification detection .................................................................. 67 5.1.6 prochot# signal pin ............................................................................. 67
4 datasheet figures 1 package-level low-power states ................................................................................11 2 core low-power states .............................................................................................12 3 4-mb and fused 2-mb micro-fcpga processor package drawing (sheet 1 of 2) .................30 4 4-mb and fused 2-mb micro-fcpga processor package drawing (sheet 2 of 2) .................31 5 2-mb micro-fcpga processor package drawing (sheet 1 of 2) ........................................32 6 2-mb micro-fcpga processor package drawing (sheet 2 of 2) ........................................33 tables 1 coordination of core-level low-power states at the package level .................................11 2 voltage identification definition .... ..............................................................................17 3 bsel[2:0] encoding for bclk frequency......................................................................21 4 fsb pin groups ........................................................................................................22 5 processor absolute maximum ratings..........................................................................23 6 dc voltage and current specifications.........................................................................25 7 fsb differential bclk specifications ............................................................................26 8 agtl+ signal group dc specifications ........................................................................27 9 cmos signal group dc specifications................... .......................................................28 10 open drain signal group dc specifications .......... ........................................................28 11 the coordinates of the processor pins as viewed from the top of the package (sheet 1 of 2) ..........................................................................................................34 12 the coordinates of the processor pins as viewed from the top of the package (sheet 2 of 2) ..........................................................................................................35 13 pin listing by pin name .............................................................................................37 14 pin listing by pin number ..........................................................................................44 15 signal description.....................................................................................................53 16 power specifications for the intel celeron dual-core processor - standard voltage ............61 17 thermal diode interface ............................................................................................62 18 thermal diode parameters using diode model ..............................................................63 19 thermal diode parameters using transistor model ... .....................................................64 20 thermal diode ntrim and diode correction toffset ........................................................65
datasheet 5 revision history document number revision number description date 321111 -001 ? initial release november 2008 321111 -002 ? added t3000, t3100, t3300, and t3500 processors june 2009 321111 -003 ? added specifications fo r sff processor su2300 ? added c4 state support information for su2300 sff processor ? added speedstep technology suppport information for su2300 sff processor ?details: ? chapter 1 : updated feature list for sff processor ? section 2.1 : added c4/deeper slee p state information ? figure 1 : updated c4/deeper sl eep state information ? figure 2 : updated c4/deeper sl eep state information ? ta b l e 1 : added c4/deeper slee p state information ?section section 2.1.1.6 , section 2.1.2.6 : added c4/deeper sleep state information ? section 2.2 : added information on intel speedstep technology description ? ta b l e 8 : added table for su2300 processor dc specifications ? ta b l e 2 5 : added table for su2300 thermal specifications ? figure 7 , ta b l e 1 9 , ta b l e 2 0 , ta b l e 1 7 , ta b l e 2 3 added su2300 pin and package information september 2009
6 datasheet
datasheet 7 introduction 1 introduction this document provides electrical, mechanical, and thermal specifications for the intel? celeron? mobile processor dual-core t1x00, intel(r) celeron processors t3x00 and intel(r) celeron dual-core sff proces sors. the processor supports the mobile intel? 4 series express chipset and inte l? 82801ibm (ich9m) controller-hub based systems. note: in this document, the celeron processor is referred to as the processor and mobile intel? 4 series express chipset family is referred to as the (g)mch. the following list provides some of the key features on this processor: ? dual-core processor for mobile with enhanced performance ? intel architecture with intel? wide dynamic execution ? l1 cache to cache (c2c) transfer ? on-die, primary 32-kb instruction cache and 32-kb write-back data cache in each core ? on-die, 1-mb second level shared cache with advanced transfer cache architecture ? streaming simd extensions 2 (sse2), streaming simd extensions 3 (sse3) and supplemental streaming simd extensions 3 (ssse3) ? 667-mhz source-synchronous front side bus (fsb) for the t1x00 series, and 800- mhz source-synchronous front side bus (fsb) for the t3x00 series processors and sff processors ? digital thermal sensor (dts) ? intel? 64 technology ? psi2 functionality ? execute disable bit support for enhanced security ? half ratio support (n/2) for core to bus ratio ? supports enhanced intel? virtualizat ion technology (sff processor only) ? intel? deeper sleep low-power state with p_lvl4 i/o support (sff processor only) ? advanced power management feature in cludes enhanced intel speedstep? technology (sff processor only)
introduction 8 datasheet 1.1 terminology term definition # a ?#? symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driv en to a low level. for example, when reset# is low, a reset has been requ ested. conversely, when nmi is high, a nonmaskable interrupt has occurred. in the case of signals where the name does not imply an active state but descri bes part of a binary sequence (such as address or data ), the ?#? symbol implies that the signal is inverted. for example, d[3:0] = ?hlh l? refers to a hex ?a?, and d[3:0]# = ?lhlh? also refers to a hex ?a? (h= high logic level, l= low logic level). xxxx means that the specification or value is yet to be determined. front side bus (fsb) refers to the interface between the processor and system core logic (also known as the chipset components). agtl+ advanced gunning transceiver logic. used to refer to assisted gtl+ signaling technology on some intel processors. storage conditions refers to a non-operational state. the processor may be installed in a platform, in a tray, or loose. proce ssors may be sealed in packaging or exposed to free air. under these condit ions, processor landings should not be connected to any suppl y voltages, have any i/os biased or receive any clocks. upon exposure to ?free air? (i.e., unsealed packaging or a device removed from packaging material) th e processor must be handled in accordance with moisture sensitivity labeling (msl) as indicated on the packaging material. enhanced intel speedstep? technology technology that provides power ma nagement capabili ties to laptops. processor core processor core die with integrated l1 and l2 cache. al l ac timing and signal integrity specifications are at the pads of the processor core. intel? 64 technology 64-bit memory extensions to the ia-32 architecture. intel? virtualization technology processor virtualization which when used in conjunction with virtual machine monitor software enables mult iple, robust independent software environments inside a single platform. tdp thermal design power v cc the processor core power supply v ss the processor ground
datasheet 9 introduction 1.2 references material and concepts available in the fo llowing documents may be beneficial when reading this document. document document number intel? celeron? dual-core t1x00 processors specification update for platforms based on mobile inte l? 4 series express chipset family see http:// www.intel.com/design/ mobile/specupdt/ 319734.htm mobile intel? 4 series expr ess chipset family datasheet 355969 mobile intel? 4 series express chipset family specification update 320123 intel? i/o controller hub 9(ich9)/ i/o controller hub 9m (ich9m) datasheet see http:// www.intel.com/assets/ pdf/datasheet/ 316972.pdf intel? i/o controller hub 8 (ich8) / i/o controller hub 8m (ich8m) specification update see http:// www.intel.com/assets/ pdf/specupdate/ 316973.pdf intel? 64 and ia-32 architecture s software developer?s manual see http:// www.intel.com/design/ pentium4/manuals/ index_new.htm intel? 64 and ia-32 architecture s software developer's manuals documentation change see http:// developer.intel.com/ design/processor/ specupdt/252046.htm volume 1: basic architecture 253665 volume 2a: instructio n set reference, a-m 253666 volume 2b: instructio n set reference, n-z 253667 volume 3a: system programming guide 253668 volume 3b: system programming guide 253669
introduction 10 datasheet
datasheet 11 low power features 2 low power features 2.1 clock control and low power states the processor supports the c1/autohalt, c1 /mwait, c2, c3 and some support the c4 core low-power states, along with their corresponding package-level states for power management. see chapter 3 to see if c4 is supported. these package states include normal, stop grant, stop grant snoop, sleep, and deep sleep. the processor?s central power management logic enters a package low-power state by initiating a p_lvlx (p_lvl2, p_lvl3, p_lvl4) i/o read to the (g)mch. figure 1 shows the package-level low-power states and figure 2 shows the core low-power states. refer to ta b l e 1 for a mapping of core low-power states to package low-power states. the processor implements two software interfaces for requesting low-power states: mwait instruction extensions with sub-state hints and p_lvlx reads to the acpi p_blk register block mapped in the processor?s i/ o address space. the p_lvlx i/o reads are converted to equivalent mwait c-state re quests inside the processor and do not directly result in i/o reads on the processor fsb. the monitor address does not need to be setup before using the p_lvlx i/o read interface. the sub-state hints used for each p_lvlx read can be configured throug h the ia32_misc_enables model specific register (msr). if the processor encounters a chipset break event while stpclk# is asserted, it asserts the pbe# output signal. assertion of pbe# when stpclk# is asserted indicates to system logic that the processor should return to the normal state. note: autohalt or mwait/c1 table 1. coordination of core-level lo w-power states at the package level core states package states c0 normal c1 (1) normal c2 stop grant c3 deep sleep c4 deeper sleep figure 1. package-level low-power states stop grant snoop normal stop grant deep sleep stpclk# asserted snoop serviced snoop occurs deeper sleep ? sleep slp# asserted slp# deasserted dpslp# asserted dpslp# deasserted dprstp# deasserted dprstp# asserted stpclk# deasserted ? ? deeper sleep includes the deeper sleep state and deep c4 sub-state
low power features 12 datasheet 2.1.1 core low-power states 2.1.1.1 c0 state this is the normal operating state of the processor. 2.1.1.2 c1/autohalt powerdown state c1/autohalt is a low-power state entered when the processor core executes the halt instruction. the processor core transitions to the c0 state upon the occurrence of smi#, init#, lint[1:0] (nmi, intr), or fsb interrupt message. reset# causes the processor to immediately initialize itself. a system management interrupt (smi) a sy stem management interrupt (smi) handler returns execution to either normal state or the c1/autohalt powerdown state. see the intel ? 64 and ia-32 intel ? architecture software develo per's manual, volume 3a/3b: system programmer's guide for more information. the system can generate a stpclk# while the processor is in the c1/autohalt powerdown state. when the system deasse rts the stpclk# interrupt, the processor returns execution to the halt state. the processor in c1/autohalt powerdown state process only the bus snoops. the processor enters a snoopable sub-state (not shown in figure 2 ) to process the snoop and then return to the c1 /autohalt powerdown state. figure 2. core low-power states c2 ? c0 stop grant core state break p_lvl2 or mwait(c2) c3 ? core state break p_lvl3 or mwait(c3) c1/mwait core state break mwait(c1) c1/auto halt halt break hlt instruction c4 ? ? core state break p_lvl4 mwait(c4) stpclk# deasserted stpclk# asserted stpclk# deasserted stpclk# asserted stpclk# deasserted stpclk# asserted break = a20m# transition, init#, intr, nmi, preq#, reset#, smi#, or apic interrupt e state break = (halt break or monitor event) and stpclk# high (not asserted) stpclk # assertion and de-assertion have no effect if a core is in c2, c3, or c4. core c 4 state supports the package level deep c4 sub-state.
datasheet 13 low power features 2.1.1.3 c1/mwait powerdown state c1/mwait is a low-power state entered when the processor core executes the mwait instruction. processor behavior in the c1/m wait state is identical to the c1/autohalt state except that there is an additional event that can cause the processor core to return to the c0 state: the monitor event. see the intel ? 64 and ia-32 intel ? architecture software developer's manual, volume 2a/2b: instruction set reference for more information. 2.1.1.4 core c2 state the core of the processor can enter the c2 st ate by initiating a p_lvl2 i/o read to the p_blk or an mwait(c2) instruction, but the processor does not issue a stop grant acknowledge special bus cycle unless the stpclk# pin is also asserted. the processor in c2 state processes only the bus snoops. the processor enters a snoopable sub-state (not shown in figure 2 ) to process the snoop and then return to the c2 state. 2.1.1.5 core c3 state core c3 state is a very low-power state the processor core can enter while maintaining context. the core of the processor can enter the c3 state by initiating a p_lvl3 i/o read to the p_blk or an mwait(c3) instruct ion. before entering the c3 state, the processor core flushes the contents of its l1 cache into the processor?s l2 cache. except for the caches, the processor core maintains all its architectural state in the c3 state. the monitor remains armed if it is co nfigured. all of the clocks in the processor core are stopped in the c3 state. because the core?s caches are flushed, the processor keeps the core in the c3 state when the processor detects a snoop on the fsb. the processor core transitions to the c0 state upon the occurrence of a monitor ev ent, smi#, init#, lint[1:0] (nmi, intr), or fsb interrupt message. reset# causes the processor core to immediately initialize itself. 2.1.1.6 core c4 state individual cores of the dual-core processor that have c4 can enter the c4 state by initiating a p_lvl4 i/o read to the p_blk or an mwait(c4) instruction. the processor core behavior in the c4 state is nearly iden tical to the behavior in the c3 state. the only difference is that if both processor cores are in c4, the central power management logic will request that the entire processo r enter the deeper sleep package low-power state (see section 2.1.2.6 ) 2.1.2 package low-power states package level low-power states are applicable to the processor. 2.1.2.1 normal state this is the normal operating state for the processor. the processor enters the normal state when the core is in the c0, c1/autohalt, or c1/mwait state. 2.1.2.2 stop-grant state when the stpclk# pin is asserted the core of the processor enters the stop-grant state within 20 bus clocks after the response phase of the processor-issued stop grant acknowledge special bus cycle. when the stpclk# pin is deasserted the core returns to the previous core low-power state.
low power features 14 datasheet since the agtl+ signal pins receive power from the fsb, these pins should not be driven (allowing the level to return to v ccp ) for minimum power drawn by the termination resistors in this state. in addition, all other input pins on the fsb should be driven to the inactive state. reset# causes the processor to immediately in itialize itself, but the processor stays in stop-grant state. when reset# is assert ed by the system the stpclk#, slp#, and dpslp# pins must be deasserted more than 480 s prior to reset# deassertion (ac specification t45). when re-entering the stop-grant state from the sleep state, stpclk# should be deasserted ten or more bus clocks after the deassertion of slp# (ac specification t75). while in the stop-grant state, the processor services snoops and latch interrupts delivered on the fsb. the processor latche s smi#, init# and lint[1:0] interrupts and services only upon return to the normal state. the pbe# signal may be driven when the pr ocessor is in stop-grant state. pbe# is asserted if there is any pending interrupt or monitor event latched within the processor. pending interrupts that are blocked by the eflags.if bit being clear still cause assertion of pbe#. assertion of pbe# indicates to system logic that the processor should return to the normal state. a transition to the stop grant snoop state occurs when the processor detects a snoop on the fsb (see section 2.1.2.3 ). a transition to the sleep state (see section 2.1.2.4 ) occurs with the assertion of the slp# signal. 2.1.2.3 stop grant snoop state the processor responds to snoop or interrupt transactions on the fsb while in stop- grant state by entering the stop-grant snoop state. the processor stays in this state until the snoop on the fsb has been serviced (whether by the processor or another agent on the fsb) or the interrupt has been latched. the processor returns to the stop- grant state once the snoop has been serviced or the interrupt has been latched. 2.1.2.4 sleep state the sleep state is a low-power state in which the processor maintains its context, maintains the phase-locked loop (pll), and st ops all internal clocks. the sleep state is entered through assertion of the slp# signal while in the stop-grant state. the slp# pin should only be asserted when the processor is in the stop-grant state. slp# assertions while the processor is not in the stop-grant state is out of specification and may result in unap proved operation. in the sleep state, the processor is incapabl e of responding to snoop transactions or latching interrupt signals. no transitions or assertions of signals (with the exception of slp#, dpslp# or reset#) are allowed on the fsb while the processor is in sleep state. snoop events that occur while in sleep state or during a transition into or out of sleep state causes unpredictable behavior. any transition on an input signal before the processor has returned to the stop-grant state results in unpredictable behavior. if reset# is driven active while the processor is in the sleep state, and held active as specified in the reset# pin sp ecification, then the processor resets itself, ignoring the transition through stop-grant state. if reset# is driven active while the processor is in the sleep state, the slp# and stpclk# signal s should be deasserted immediately after reset# is asserted to ensure the proce ssor correctly executes the reset sequence. while in the sleep state, the processor is capable of entering an even lower power state, the deep sleep state, by asserting the dpslp# pin. (see section 2.1.2.5 .) while the processor is in the sleep state, the slp# pin must be deasserted if another asynchronous fsb event needs to occur.
datasheet 15 low power features 2.1.2.5 deep sleep state deep sleep state is a very low-power state the processor can enter while maintaining context. deep sleep state is entered by a sserting the dpslp# pi n while in the sleep state. bclk may be stopped during the deep sleep state for additional platform level power savings. bclk stop/restart timings on appropriate chipset based platforms with the ck505 clock chip are as follows: ? deep sleep entry: the system clock chip may stop/tristate bclk within 2 bclks of dpslp# assertion. it is permissible to leave bclk running during deep sleep. ? deep sleep exit: the system clock chip must drive bclk to differential dc levels within 2-3 ns of dpslp# deassertion an d start toggling bclk within 10 bclk periods. to re-enter the sleep state, the dpslp# pin must be deasserted. bclk can be re- started after dpslp# deassertion as described above. a period of 15 microseconds (to allow for pll stabilization) must occur before the processor can be considered to be in the sleep state. once in the sleep state, the slp# pin must be deasserted to re-enter the stop-grant state. while in deep sleep state, the processo r is incapable of responding to snoop transactions or latching interrupt signals. no transitions of signals are allowed on the fsb while the processor is in deep sleep state. any transition on an input signal before the processor has returned to stop-grant state results in unpredictable behavior. 2.1.2.6 deeper sleep state the deeper sleep state is similar to the deep sleep state but further reduces core voltage levels. one of the potential lower core voltage levels is achieved by entering the base deeper sleep state. the deeper sleep state is entered through assertion of the dprstp# pin while in the deep sleep state. the following lower core voltage level is achieved by entering the intel enhanced deeper sleep state which is a sub-state of deeper sleep state. intel enhanced deeper sleep state is entered through assertion of the dprstp# pin while in the deep sleep only when the l2 cache has been completely shut down. exit from deeper sleep is initiated by dprs tp# deassertion when either core requests a core state other than c4 or either core requests a processor performance state other than the lowest operating point. 2.2 enhanced intel speedstep? technology some processors feature enhanced intel speedstep technology. see each processor?s dcl to see if it supports enhanced intel speedstep technology. following are the key features of enhanced in tel speedstep technology: ? multiple voltage and frequency operating points provide optimal performance at the lowest power. ? voltage and frequency selection is software-controlled by writing to processor msrs: ? if the target frequency is higher than the current frequency, v cc is ramped up in steps by placing new values on the vid pins, and the pll then locks to the new frequency. ? if the target frequency is lower than th e current frequency, the pll locks to the new frequency and the v cc is changed through the vid pin mechanism. ? software transitions are accepted at any time. if a previous transition is in progress, the new transition is deferred until the previous transition completes.
low power features 16 datasheet ? the processor controls voltage ramp rates internally to ensure glitch-free transitions. ? low transition latency and large number of transitions possible per second: ? processor core (including l2 cache) is unavailable for up to 10 s during the frequency transition. ? the bus protocol (bnr# mechanism) is used to block snooping. ? improved intel? thermal monitor mode: ? when the on-die thermal sensor indicates that the die temperature is too high the processor can automatically perform a transition to a lower frequency and voltage specified in a software-programmable msr. ? the processor waits for a fixed time period. if the die temperature is down to acceptable levels, an up-transition to the previous frequency and voltage point occurs. ? an interrupt is generated for the up and down intel thermal monitor transitions enabling better system-level thermal management. ? enhanced thermal management features: ? digital thermal sensor and out of specification detection. ? intel thermal monitor 1 (tm1) in addition to intel thermal monitor 2 (tm2) in case of unsuccessful tm2 transition. ? dual core thermal management synchronization. each core in the dual-core processor impl ements an independent msr for controlling enhanced intel speedstep technology, but both cores must operate at the same frequency and voltage. the processor has performance state coordination logic to resolve frequency and voltage requests from the two cores into a single frequency and voltage request for the package as a whole. if both cores request the same frequency and voltage, then the processor will transi tion to the requested common frequency and voltage. if the two cores have different frequency and voltage requests, then the processor will take the highest of the two frequencies and voltages as the resolved request and transition to that frequency and voltage. caution: enhanced intel speedstep technology transitions are multistep processes that require clocked control. these transitions cannot occur when the processor is in the sleep or deep sleep package low-power states since processor clocks are not active in these states. 2.3 low-power fsb features the processor incorporates fsb low-power enhancements: ? dynamic on die termination disabling ?low v ccp (i/o termination voltage) the on die termination on the processor fsb buffers is disabled when the signals are driven low, resulting in power savings. the low i/o termination voltage is on a dedicated voltage plane independent of the core voltage, enabling low i/o switching power at all times.
datasheet 17 low power features 2.4 processor power status indicator (psi#) signal the psi# signal is asserted when the processor is in a reduced power consumption state. psi# can be used to improve light load efficiency of the voltage regulator, resulting in platform power savings and exte nded battery life. the algorithm that the processor uses for determining when to asse rt psi# is different from the algorithm used in previous processors.
low power features 18 datasheet
datasheet 19 electrical specifications 3 electrical specifications 3.1 power and ground pins for clean, on-chip power distribution, the processor has a large number of v cc (power) and v ss (ground) inputs. all power pins must be connected to v cc power planes while all v ss pins must be connected to system ground planes. use of multiple power and ground planes is recommended to reduce i*r drop. the processor v cc pins must be supplied the voltage determined by the vid (voltage id) pins. 3.2 fsb clock (bclk[1:0] ) and processor clocking bclk[1:0] directly controls the fsb interface speed as well as the core frequency of the processor. as in previous generation processors, the processor core frequency is a multiple of the bclk[1:0] frequency. the processor uses a differential clocking implementation. 3.3 voltage identification the processor uses seven voltage identification pins,vid[6:0], to support automatic selection of power supply voltages. the vid pins for processor are cmos outputs driven by the processor vid circuitry. ta b l e 2 specifies the voltage level corresponding to the state of vid[6:0]. a 1 refers to a high-voltage level and a 0 refers to low-voltage level. table 2. voltage identification definition (sheet 1 of 4) vid6 vid5 vid4 vid3 vid2 vid1 vid0 v cc (v) 0 0 0 0 0 0 0 1.5000 0 0 0 0 0 0 1 1.4875 0 0 0 0 0 1 0 1.4750 0 0 0 0 0 1 1 1.4625 0 0 0 0 1 0 0 1.4500 0 0 0 0 1 0 1 1.4375 0 0 0 0 1 1 0 1.4250 0 0 0 0 1 1 1 1.4125 0 0 0 1 0 0 0 1.4000 0 0 0 1 0 0 1 1.3875 0 0 0 1 0 1 0 1.3750 0 0 0 1 0 1 1 1.3625 0 0 0 1 1 0 0 1.3500 0 0 0 1 1 0 1 1.3375 0 0 0 1 1 1 0 1.3250 0 0 0 1 1 1 1 1.3125 0 0 1 0 0 0 0 1.3000 0 0 1 0 0 0 1 1.2875 0 0 1 0 0 1 0 1.2750 0 0 1 0 0 1 1 1.2625 0 0 1 0 1 0 0 1.2500 0 0 1 0 1 0 1 1.2375
electrical specifications 20 datasheet 0 0 1 0 1 1 0 1.2250 0 0 1 0 1 1 1 1.2125 0 0 1 1 0 0 0 1.2000 0 0 1 1 0 0 1 1.1875 0 0 1 1 0 1 0 1.1750 0 0 1 1 0 1 1 1.1625 0 0 1 1 1 0 0 1.1500 0 0 1 1 1 0 1 1.1375 0 0 1 1 1 1 0 1.1250 0 0 1 1 1 1 1 1.1125 0 1 0 0 0 0 0 1.1000 0 1 0 0 0 0 1 1.0875 0 1 0 0 0 1 0 1.0750 0 1 0 0 0 1 1 1.0625 0 1 0 0 1 0 0 1.0500 0 1 0 0 1 0 1 1.0375 0 1 0 0 1 1 0 1.0250 0 1 0 0 1 1 1 1.0125 0 1 0 1 0 0 0 1.0000 0 1 0 1 0 0 1 0.9875 0 1 0 1 0 1 0 0.9750 0 1 0 1 0 1 1 0.9625 0 1 0 1 1 0 0 0.9500 0 1 0 1 1 0 1 0.9375 0 1 0 1 1 1 0 0.9250 0 1 0 1 1 1 1 0.9125 0 1 1 0 0 0 0 0.9000 0 1 1 0 0 0 1 0.8875 0 1 1 0 0 1 0 0.8750 0 1 1 0 0 1 1 0.8625 0 1 1 0 1 0 0 0.8500 0 1 1 0 1 0 1 0.8375 0 1 1 0 1 1 0 0.8250 0 1 1 0 1 1 1 0.8125 0 1 1 1 0 0 0 0.8000 0 1 1 1 0 0 1 0.7875 0 1 1 1 0 1 0 0.7750 0 1 1 1 0 1 1 0.7625 0 1 1 1 1 0 0 0.7500 0 1 1 1 1 0 1 0.7375 0 1 1 1 1 1 0 0.7250 0 1 1 1 1 1 1 0.7125 1 0 0 0 0 0 0 0.7000 1 0 0 0 0 0 1 0.6875 1 0 0 0 0 1 0 0.6750 1 0 0 0 0 1 1 0.6625 1 0 0 0 1 0 0 0.6500 table 2. voltage identification definition (sheet 2 of 4) vid6 vid5 vid4 vid3 vid2 vid1 vid0 v cc (v)
datasheet 21 electrical specifications 1 0 0 0 1 0 1 0.6375 1 0 0 0 1 1 0 0.6250 1 0 0 0 1 1 1 0.6125 1 0 0 1 0 0 0 0.6000 1 0 0 1 0 0 1 0.5875 1 0 0 1 0 1 0 0.5750 1 0 0 1 0 1 1 0.5625 1 0 0 1 1 0 0 0.5500 1 0 0 1 1 0 1 0.5375 1 0 0 1 1 1 0 0.5250 1 0 0 1 1 1 1 0.5125 1 0 1 0 0 0 0 0.5000 1 0 1 0 0 0 1 0.4875 1 0 1 0 0 1 0 0.4750 1 0 1 0 0 1 1 0.4625 1 0 1 0 1 0 0 0.4500 1 0 1 0 1 0 1 0.4375 1 0 1 0 1 1 0 0.4250 1 0 1 0 1 1 1 0.4125 1 0 1 1 0 0 0 0.4000 1 0 1 1 0 0 1 0.3875 1 0 1 1 0 1 0 0.3750 1 0 1 1 0 1 1 0.3625 1 0 1 1 1 0 0 0.3500 1 0 1 1 1 0 1 0.3375 1 0 1 1 1 1 0 0.3250 1 0 1 1 1 1 1 0.3125 1 1 0 0 0 0 0 0.3000 1 1 0 0 0 0 1 0.2875 1 1 0 0 0 1 0 0.2750 1 1 0 0 0 1 1 0.2625 1 1 0 0 1 0 0 0.2500 1 1 0 0 1 0 1 0.2375 1 1 0 0 1 1 0 0.2250 1 1 0 0 1 1 1 0.2125 1 1 0 1 0 0 0 0.2000 1 1 0 1 0 0 1 0.1875 1 1 0 1 0 1 0 0.1750 1 1 0 1 0 1 1 0.1625 1 1 0 1 1 0 0 0.1500 1 1 0 1 1 0 1 0.1375 1 1 0 1 1 1 0 0.1250 1 1 0 1 1 1 1 0.1125 1 1 1 0 0 0 0 0.1000 1 1 1 0 0 0 1 0.0875 1 1 1 0 0 1 0 0.0750 1 1 1 0 0 1 1 0.0625 table 2. voltage identification definition (sheet 3 of 4) vid6 vid5 vid4 vid3 vid2 vid1 vid0 v cc (v)
electrical specifications 22 datasheet 3.4 catastrophic thermal protection the processor supports the thermtrip# signal for catastrophic thermal protection. an external thermal sensor should also be used to protect the processor and the system against excessive temperatures. even with the activation of thermtrip#, which halts all processor internal clocks and activity, le akage current can be high enough that the processor cannot be protected in all conditions without power removal to the processor. if the external thermal sensor detects a catastrophic processor temperature of 125 c (maximum), or if the thermtri p# signal is asserted, the v cc supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway of the processor. thermtrip# functionality is not guaranteed if the pwrgood signal is not asserted. 3.5 reserved and unused pins all reserved (rsvd) pins must remain un connected. connection of these pins to v cc , v ss , or to any other signal (including each other) may result in component malfunction or incompatibility with future processors. see section 4.2 for a pin listing of the processor and the location of all rsvd pins. for reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level. unused active low agtl+ inputs may be left as no connects if agtl+ termination is provided on the proc essor silicon. unused active high inputs should be connected through a resistor to ground (v ss ). unused outputs can be left unconnected. the test1 and test2 pins must have a stuffing option of separate pull-down resistors to v ss . for the purpose of testability, route the test3 and test5 signals through a ground- referenced zo = 55- trace that ends in a via that is near a gnd via and is accessible through an oscilloscope connection. 1 1 1 0 1 0 0 0.0500 1 1 1 0 1 0 1 0.0375 1 1 1 0 1 1 0 0.0250 1 1 1 0 1 1 1 0.0125 1 1 1 1 0 0 0 0.0000 1 1 1 1 0 0 1 0.0000 1 1 1 1 0 1 0 0.0000 1 1 1 1 0 1 1 0.0000 1 1 1 1 1 0 0 0.0000 1 1 1 1 1 0 1 0.0000 1 1 1 1 1 1 0 0.0000 1 1 1 1 1 1 1 0.0000 table 2. voltage identification definition (sheet 4 of 4) vid6 vid5 vid4 vid3 vid2 vid1 vid0 v cc (v)
datasheet 23 electrical specifications 3.6 fsb frequency select signals (bsel[2:0]) the bsel[2:0] signals are used to select the frequency of the processor input clock (bclk[1:0]). these signals should be connected to the clock chip and the appropriate chipset on the platform. the bsel encoding for bclk[1:0] is shown in ta b l e 3 . 3.7 fsb signal groups the fsb signals have been combined into groups by buffer ty pe in the following sections. agtl+ input signals have differential input buffers, which use gtlref as a reference level. in this document, the term ?agtl+ input? refers to the agtl+ input group as well as the agtl+ i/o group when re ceiving. similarly, ?agtl+ output? refers to the agtl+ output group as well as the agtl+ i/o group when driving. with the implementation of a source synchronous data bus, two sets of timing parameters need to be specified. one se t is for common clock signals, which are dependent upon the rising edge of bclk0 (ads#, hit#, hitm#, etc.) and the second set is for the source synchronous signals, which are relative to their respective strobe lines (data and address) as well as the risi ng edge of bclk0. as ychronous signals are still present (a20m#, ignne#, etc.) and can become active at any time during the clock cycle. ta b l e 4 identifies which signals are common clock, source synchronous, and asynchronous. table 3. bsel[2:0] encoding for bclk frequency bsel[2] bsel[1] bsel [0] bclk frequency l l l reserved l l h 133 mhz l h h reserved l h l 200 mhz h h l reserved h h h reserved h l h reserved h l l reserved
electrical specifications 24 datasheet notes: 1. refer to chapter 4 for signal descriptions an d termination requirements. 2. in processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. in system s with the debug port im plemented on the system board, these signals are no connects. 3. bpm[2:1]# and prdy# are ag tl+ output only signals. 4. prochot# signal type is open drain output and cmos input. 5. on die termination differs from other agtl+ signals. table 4. fsb pin groups signal group type signals 1 agtl+ common clock input synchronous to bclk[1:0] bpri#, defer#, preq# 5 , reset#, rs[2:0]#, trdy# agtl+ common clock i/o synchronous to bclk[1:0] ads#, bnr#, bpm[3:0]# 3 , br0#, dbsy#, drdy#, hit#, hitm#, lock#, prdy# 3 , dpwr# agtl+ source synchronous i/o synchronous to assoc. strobe agtl+ strobes synchronous to bclk[1:0] adstb[1:0]#, dstbp[3:0]#, dstbn[3:0]# cmos input asynchronous a20m#, dprstp#, dpslp#, ignne#, init#, lint0/intr, lint1/nmi, pwrgood, smi#, slp#, stpclk# open drain output asynchronous ferr#, ierr#, thermtrip# open drain i/o asynchronous prochot# 4 cmos output asynchronous psi#, vid[6:0], bsel[2:0] cmos input synchronous to tck tck, tdi, tms, trst# open drain output synchronous to tck tdo fsb clock clock bclk[1:0] power/other comp[3:0], dbr# 2 , gtlref, rsvd, test2, test1, thermda, thermdc, v cc , v cca , v ccp, v cc_sense , v ss, v ss_sense signals associated strobe req[4:0]#, a[16:3]# adstb[0]# a[35:17]# adstb[1]# d[15:0]#, dinv0# dstbp0#, dstbn0# d[31:16]#, dinv1# dstbp1#, dstbn1# d[47:32]#, dinv2# dstbp2#, dstbn2# d[63:48]#, dinv3# dstbp3#, dstbn3#
datasheet 25 electrical specifications 3.8 cmos signals cmos input signals are shown in ta b l e 4 . legacy output ferr#, ierr# and other non- agtl+ signals (thermtrip# and prochot#) ut ilize open drain output buffers. these signals do not have setup or hold time specif ications in relation to bclk[1:0]. however, all of the cmos signals are required to be asserted for more than four bclks in order for the processor to recognize them. see section 3.10 for the dc specifications for the cmos signal groups. 3.9 maximum ratings ta b l e 5 specifies absolute maximum and minimum ratings. if the processor stays within functional operation limits, functionality and long-term reliability can be expected. caution: at conditions outside functional operatio n condition limits, but within absolute maximum and minimum ratings, neither functionality nor long term reliability can be expected. at conditions exceeding absolu te maximum and minimum ratings, neither functionality nor long term reliability can be expected. caution: precautions should always be taken to avoid high-static voltages or electric fields. notes: 1. for functional operation, all processor electr ical, signal quality, mechanical and thermal specifications must be satisfied. 2. storage temperature is applic able to storage conditions only. in this scenario, the processor must not receive a clock, and no lands can be connected to a voltage bias. storage within these limits do es not affect the long term reliability of the device. for functional operation, please refer to the processor case temperature specifications. 3. this rating applies to th e processor and does not include any tray or packaging. 4. failure to adhere to this specification can affect the long-term reliability of the processor. table 5. processor absolute maximum ratings symbol parameter min max unit notes 1 t storage processor storage temperature -40 85 c 2, 3, 4 v cc any processor supply voltage with respect to v ss -0.3 1.55 v v inagtl+ agtl+ buffer dc input voltage with respect to v ss -0.1 1.55 v v inasynch_cmos cmos buffer dc input voltage with respect to v ss -0.1 1.55 v
electrical specifications 26 datasheet 3.10 processor dc specifications the processor dc specifications in this section are define d at the processor core (pads) unless noted otherwise . see ta b l e 4 for the pin signal definitions and signal pin assignments. ta b l e 7 through ta b l e 1 0 list the dc specifications for the processor and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. the highest frequency mode (hfm) and super low frequency mode (superlfm) refer to the highest and lowest core operating frequencies supported on the processor. active mode load line specificat ions apply in all states except in the deep sleep and deeper sleep states. v cc,boot is the default voltage driven by the voltage regulator at power up in order to set the vid values. unless specified otherwise, all specifications for the processor are at tjunction = 100 c. care should be taken to read all notes associated with each parameter.
datasheet 27 electrical specifications notes: 1. each processor is programmed with a maximum valid voltage identification value (vid), which is set at manufacturing and cannot be altered. individual maximum vid values ar e calibrated during manufacturing in such a way that two processors at the same frequency may have differe nt settings within the vid range. note that this differs from the vid employed by th e processor during a power management event (intel thermal monitor 2, or extended halt state). 2. the voltage specifications are as sumed to be measured across v cc_sense and v ss_sense pins at socket with a 100-mhz bandwidth oscill oscope, 1.5-pf maximum pr obe capacitance, and 1-m minimum impedance. the maximum length of ground wire on the probe shou ld be less than 5 mm. en sure external noise from the system is not coupled in the scope probe. 3. specified at 105 c tj. 4. specified at the nominal v cc . 5. 800-mhz fsb supported 6. instantaneous current i cc_core_inst of 55 a has to be sustained for short time (t inst ) of 10 s. average current is less than maximum specified i ccdes . vr ocp threshold should be hi gh enough to support current levels described herein. 7. measured at the bulk capa citors on the motherboard. 8. based on simulations and averaged over the durati on of any change in curre nt. specified by design/ characterization at nominal v cc . not 100% tested. 9. this is a power-up peak current spec ification, which is applicable when v ccp is high and v cc_core is low. 10. this is a steady-state i cc current specification, which is applicable when both v ccp and v cc_core are high. 1-mb l2 cache. table 6. dc voltage and current specific ations for the t3x00 celeron processors symbol parameter min typ max unit notes v cc v cc of the processor core 0.8 1.25 v 1, 2 v cc,boot default v cc voltage for initial power up 1.20 v 2, 8 v ccp agtl+ termination voltage 1.00 1.05 1.10 v v cca pll supply voltage 1.425 1.5 1.575 v i ccdes i cc for processors recommended design targets: 47 a 5 i cc i cc for processors a processor number frequency die variant t3000 1.8 ghz 1 mb 47 a 3, 4 t3100 1.9 ghz 1 mb 47 a 3, 4 i ah , i sgnt i cc auto-halt & stop-grant 25.4 a 3, 4 i slp i cc sleep 24.7 a 3, 4 i dslp i c c deep sleep 22.9 a 3, 4 di cc/dt v cc power supply current slew rate at cpu package pin 600 a/s 6, 7 i cca i cc for v cca supply 130 ma i ccp i cc for v ccp supply before v cc stable i cc for v ccp supply after v cc stable 4.5 2.5 a a 9 10
electrical specifications 28 datasheet notes: 1. each processor is programmed with a maximum valid vo ltage identification value (vid), which is set at manufacturing and cannot be altered. individual maxi mum vid values are calibrated during manufacturing in such a way that two processors at the same frequen cy may have different settings within the vid range. note that this differs from the vid employed by th e processor during a power management event (intel thermal monitor 2, or extended halt state). 2. the voltage specifications are assumed to be measured across v cc_sense and v ss_sense pins at socket with a 100-mhz bandwidth oscilloscope, 1.5-pf maximum probe capacitance, and 1-m minimum impedance. the maximum length of ground wire on the probe shou ld be less than 5 mm. en sure external noise from the system is not coupled in the scope probe. 3. specified at 100 c tj. 4. specified at the nominal v cc . 5. 667-mhz fsb supported 6. instantaneous current i cc_core_inst of 55 a has to be sustained for short time (t inst ) of 10 s. average current is less than maximum specified i ccdes . vr ocp threshold should be high enough to support current levels descri bed herein. 7. measured at the bulk capacitors on the motherboard. 8. based on simulations and averaged over the durati on of any change in current. specified by design/ characterization at nominal v cc . not 100% tested. 9. this is a power-up peak current specification, which is applicable when v ccp is high and v cc_core is low. 10. this is a steady-state i cc current specification, which is applicable when both v ccp and v cc_core are high. 11. 512-kb l2 cache. table 7. dc voltage and current specific ations for the t1x00 celeron mobile processors symbol parameter min typ max unit notes v cc v cc of the processor core 0.95 1.15 1.30 v 1, 2 v cc,boot default v cc voltage for initial power up 1.20 v 2, 8 v ccp agtl+ termination voltage 1.00 1.05 1.10 v v cca pll supply voltage 1.425 1.5 1.575 v i ccdes i cc for processors recommended design targets: 36 a 5 i cc i cc for processors a processor number frequency die variant t1600 1.66 ghz 1 mb 41 a 3, 4 t1700 1.83 ghz 1 mb 41 a 3, 4 i ah , i sgnt i cc auto-halt & stop-grant 21 a 3, 4 i slp i cc sleep 20.5 a 3, 4 i dslp i c c deep sleep 18.6 a 3, 4 di cc/dt v cc power supply current slew rate at cpu package pin 600 a/s 6, 7 i cca i cc for v cca supply 130 ma i ccp i cc for v ccp supply before v cc stable i cc for v ccp supply after v cc stable 4.5 2.5 a a 9 10
datasheet 29 electrical specifications table 8 lists the dc specifications for the processor and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. the highest frequency mode (hfm) and lowest frequency mode (lfm) refer to the highest and lowest core operating frequencies supported on the genuine intel processor. unless specified otherwise, all specifications for the processor are at tjunction =100 oc. care should be taken to read all notes associated with each parameter. notes: 1. each processor is programmed with a maximum valid voltage identification value (vid), which is set at manufacturing and can not be altered. individu al maximum vid values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the vid range. note that this differs from the vid employed by the processo r during a power management event (ex: extended halt state). 2. the voltage specifications are as sumed to be measured across v ccsense and v sssense pins at socket with a 100-mhz bandwidth oscillos cope, 1.5-pf maximum prob e capacitance, and 1-m minimum impedance. the maximum length of ground wire on the probe shou ld be less than 5 mm. en sure external noise from the system is not coupled in the scope probe. 3. specified at 100c tj. 4. specified at nominal v cc . table 8. voltage and current specifications for the ultra low voltage dual-core 1m cache intel celeron sff genuine intel processor symbol parameter min typ max unit notes v cc v cc of the processor core 0.8 1.1 v 1, 2 v cc,boot default v cc voltage for initial power up ? 1.20 ? v 2, 8 v ccp agtl+ termination voltage 1.00 1.05 1.10 v v cca pll supply voltage 1.425 1.5 1.575 v i ccdes i cc for processors recommended design target ??18a 5 i cc i cc for processors a processor number frequency die variant su2300 1.2ghz 1mb 17.6 a 3, 4 i ah, i sgnt i cc auto-halt & stop-grant ?? 6.3 a3, 4 i slp i cc sleep ?? 5.9 a3, 4 i dslp i cc deep sleep ??5.0a 3, 4 i dprslp i cc deeper sleep ??3.2a 3, 4 di cc/ dt v cc power supply current slew rate at processor package pin ? ? 600 a/s 7 i cca i cc for v cca supply ? ? 130 ma i ccp i cc for v ccp supply before v cc stable i cc for v ccp supply after v cc stable ?? 4.5 2.5 a a 8 9
electrical specifications 30 datasheet 5. 800-mhz fsb supported 6. measured at the bulk capacitors on the motherboard. 7. based on simulations and averaged over the durati on of any change in current. specified by design/ characterization at nominal v cc . not 100% tested. 8. this is a power-up peak current specification, which is applicable when v ccp is high and v cc core is low. 9. this is a steady-state icc current specification, which is applicable when both v ccp and v cc core are high. 10. su2300 processor operates at same core frequency in hfm and lfm. 1. unless otherwise noted, all specifications in this table apply to al l processor frequencies. 2. crossing voltage is defined as absolute voltag e where rising edge of bclk0 is equal to the falling edge of bclk1. 3. for vin between 0 v and v ih . 4. cpad includes die capacitance only. no package parasitics are included. 5. v cross is defined as the total variation of all crossing voltages as defined in note 2. 6. measurement taken from differential waveform. 7. measurement taken from single-ended waveform. 8. only applies to the differe ntial rising edge (clock ri sing and clock# falling). table 9. fsb differential bclk specifications symbol parameter min typ max unit notes 1 v cross crossing voltage 0.3 0.55 v 2, 7, 8 v cross range of crossing points 140 mv 2, 7, 5 v swing differential output swing 300 mv 6 i li input leakage current -5 +5 a 3 cpad pad capacitance 0.95 1.2 1.45 pf 4
datasheet 31 electrical specifications notes: 1. unless otherwise noted, all specifications in this table apply to al l processor frequencies. 2. v il is defined as the maximum voltage level at a receiving agent that is interpreted as a logical low value. 3. v ih is defined as the minimum voltage level at a receiving agent that is interpreted as a logical high value. 4. v ih and v oh may experience excursions above v ccp . however, input signal drivers must comply with the signal quality specifications. 5. this is the pull-down driver resistance. measured at 0.31*v ccp . r on (min) = 0.4*r tt , r on (typ) = 0.455*r tt , r on (max) = 0.51*r tt . r tt typical value of 55 is used for r on typ/ min/max calculations. 6. gtlref should be generated from v ccp with a 1%-tolerance resistor divider. the v ccp referred to in these specifications is the instantaneous v ccp . 7. r tt is the on-die termination resistance measured at v ol of the agtl+ output driver. measured at 0.31*v ccp . r tt is connected to v ccp on die. 8. specified with on die r tt and r on turned off. vin between 0 and v ccp . 9. cpad includes die capaci tance only. no package parasitics are included. 10. this is the external re sistor on the comp pins. 11. on die termination resist ance measured at 0.33*v ccp . table 10. agtl+ signal group dc specifications symbol parameter min typ max unit notes 1 v ccp i/o voltage 1.00 1.05 1.10 v gtlref reference voltage 2/3 v ccp v6 r comp compensation resistor 27.23 27.5 27.78 10 r odt termination resistor 55 11 v ih input high voltage gtlref+0.10 v ccp v ccp +0.10 v 3,6 v il input low voltage -0.10 0 gtlref-0.10 v 2,4 v oh output high voltage v ccp -0.10 v ccp v ccp 6 r tt termination resistance 50 55 61 7 r on buffer on resistance 22 25 28 5 i li input leakage current 100 a 8 cpad pad capacitance 1.6 2.1 2.55 pf 9
electrical specifications 32 datasheet notes: 1. unless otherwise noted, all specifications in this table apply to al l processor frequencies. 2. the v ccp referred to in these specificat ions refers to instantaneous v ccp . 3. cpad2 includes die capacitance for all other cmos input signals. no package parasitics are included. 4. measured at 0.1*v ccp . 5. measured at 0.9*v ccp . 6. for vin between 0 v and v ccp . measured when the driver is tristated. 7. cpad1 includes die capacitance only fo r dprstp#, dpslp#, pwrgood. no package parasitics are included. notes: 1. unless otherwise noted, all specifications in this table apply to al l processor frequencies. 2. measured at 0.2 v. 3. v oh is determined by value of the external pull-up resistor to v ccp . 4. for vin between 0 v and v oh . 5. cpad includes die capacitance only. no package parasitics are included. table 11. cmos signal group dc specifications symbol parameter min typ max unit notes 1 v ccp i/o voltage 1.00 1.05 1.10 v v ih input high voltage 0.7*v ccp v ccp v ccp +0.1 v 2 v il input low voltage cmos -0.10 0.00 0.3*v ccp v2 v oh output high voltage 0.9*v ccp v ccp v ccp +0.1 v 2 v ol output low voltage -0.10 0 0.1*v ccp v2 i oh output high current 1.5 4.1 ma 5 i ol output low current 1.5 4.1 ma 4 i li input leakage current 100 a 6 cpad1 pad capacitance 1.6 2.1 2.55 pf 7 cpad2 pad capacitance for cmos input 0.95 1.2 1.45 3 table 12. open drain signal group dc specifications symbol parameter min typ max unit notes 1 v oh output high voltage v ccp -5% v ccp v ccp +5% v 3 v ol output low voltage 0 0.20 v i ol output low current 16 50 ma 2 i lo output leakage current 200 a 4 cpad pad capacitance 1.9 2.2 2.45 pf 5
datasheet 33 package mechanical specifications and pin information 4 package mechanical specifications and pin information 4.1 package mechanical specifications the processor is available in a 1-mb, 47 8-pin micro-fcpga package. the package mechanical dimensions, keep-out zones, processor mass specifications, and package loading specifications are shown in figure 3 through figure 6 . the sff processor (ulv dc) is available 956-ball micro-fcbga packages. the package mechanical dimensions are shown in figure 7. the maximum outgoing co-planarity is 0.2 mm (8 mils) for sff package the mechanical package pressure specifications are in a direction normal to the surface of the processor. this requirement is to protect the processor die from fracture risk due to uneven die pressure distribution under t ilt, stack-up tolerances and other similar conditions. these specifications assume that a mechanical attach is designed specifically to load one type of processor. moreover, the processor package substrate should not be used as a mechanical reference or load-bearing surface for the th ermal or mechanical solution. please refer to the santa rosa platform mechanical design guide for more details. note: for m-step based processors refer to the 2-mb package drawings.
package mechanical specifications and pin information 34 datasheet figure 3. 4-mb and fused 2-mb micro-fcpga processor package drawing (sheet 1 of 2) h

! "#$%$ &'%( ) * * * +,- ,./0 1--1.0.2 1/ *
1
1
1
1 * )1. ! 34! 5 6
1
1

datasheet 35 package mechanical specifications and pin information figure 4. 4-mb and fused 2-mb micro-fcpga processor packag e drawing (sheet 2 of 2)

! ! "# $ %& ' (( $ %& '
package mechanical specifications and pin information 36 datasheet figure 5. 2-mb micro-fcpga processor package drawing (sheet 1 of 2)

! "#$%$ &'%( )
*
* +,- ,./0 1--1.0.2 1/ * 1 1 1 1 * )1. ! 34! 5 6 1 1

datasheet 37 package mechanical specifications and pin information figure 6. 2-mb micro-fcpga processor package drawing (sheet 2 of 2)

! ! ! ! "# $ %& ' (( $ %& '
package mechanical specifications and pin information 38 datasheet figure 7. sff (ulv dc) die micro- fcbga processor package drawing

! "#$%&%! '()* +,-!&./00 /! 1 2 2 1

345 544 44 6 4 47
1
1 2 2
? 0.14 a a b l c ? 0.04 ? 0.460.04 (metal diameter) ? 0.390.02 (solder resist opening) l 1 68 5 56565 5 5645 5 5 5 43 5 5 9 6 65+ 9 3 56 45 9 815+ 1 656 86 5 5 56565 :
2 1 4 6 + 8 ; 3 : 8 3 + ; 6 4 2 : 1

datasheet 39 package mechanical specifications and pin information 4.2 processor pinout and pin list ta b l e 1 3 shows the top view pinout of the intel celeron dual-core processor. the pin list, arranged in two different format s, is shown in the following pages. table 13. the coordinates of the processor pi ns as viewed from the top of the package (sheet 1 of 2) 1 234 5 678910111213 a vss smi# vss ferr# a20m# vcc vss vcc vcc vss vcc vcc a b rsvd init# lint1 dpslp# vss vcc vss vcc vcc vss vcc vss b c reset# vss rsvd ignne # vss lint0 therm trip# vss vcc vcc vss vcc vcc c d vss rsvd rsvd vss stpclk # pwrgo od slp# vss vcc vcc vss vcc vss d e dbsy# bnr# vss hitm# dprstp # vss vcc vss vcc vcc vss vcc vcc e f br0# vss rs[0]# rs[1]# vss rsvd vcc vss vcc vcc vss vcc vss f g vss trdy# rs[2]# vss bpri# hit# g h ads# req[1] # vss lock# defer# vss h j a[9]# vss req[3] # a[3]# vss vccp j k vss req[2] # req[0] # vss a[6]# vccp k l req[4]# a[13]# vss a[5]# a[4]# vss l m adstb[0 ]# vss a[7]# rsvd vss vccp m n vss a[8]# a[10]# vss rsvd vccp n p a[15]# a[12]# vss a[14]# a[11]# vss p r a[16]# vss a[19]# a[24]# vss vccp r t vss rsvd a[26]# vss a[25]# vccp t u a[23]# a[30]# vss a[21]# a[18]# vss u v adstb[1 ]# vss rsvd a[31]# vss vccp v w vss a[27]# a[32]# vss a[28]# a[20]# w y comp[3] a[17]# vss a[29]# a[22]# vss y aa comp[2] vss a[35]# a[33]# vss tdi vcc vss vcc vcc vss vcc vcc aa ab vss a[34]# tdo vss tms trst# vcc vss vcc vcc vss vcc vss ab ac preq# prdy# vss bpm[3] # tck vss vcc vss vcc vcc vss vcc vcc ac ad bpm[2]# vss bpm[1] # bpm[0] # vss vid[0] vcc vss vcc vcc vss vcc vss ad ae vss vid[6] vid[4] vss vid[2] psi# vss sense vss vcc vcc vss vcc vcc ae af test5 vss vid[5] vid[3] vid[1] vss vcc sense vss vcc vcc vss vcc vss af 1 234 5 678910111213
package mechanical specifications and pin information 40 datasheet table 14. the coordinates of the processor pi ns as viewed from the top of the package (sheet 2 of 2) 14 15 16 17 18 19 20 21 22 23 24 25 26 a vss vcc vss vcc vcc vss vcc bclk[1] bclk[0] vss thrmda vss test6 a b vcc vcc vss vcc vcc vss vcc vss bsel[0] bsel[1] vss thrmdc vcca b c vss vcc vss vcc vcc vss dbr# bsel[2] vss test1 test3 vss vcca c d vcc vcc vss vcc vcc vss ierr# procho t# rsvd vss dpwr# test2 vss d e vss vcc vss vcc vcc vss vcc vss d[0]# d[7]# vss d[6]# d[2]# e f vcc vcc vss vcc vcc vss vcc drdy# vss d[4]# d[1]# vss d[13]# f g vccp d[3]# vss d[9]# d[5]# vss g h vss d[12]# d[15]# vss dinv[0]# dstbp[ 0]# h j vccp vss d[11]# d[10]# vss dstbn[ 0]# j k vccp d[14]# vss d[8]# d[17]# vss k l vss d[22]# d[20]# vss d[29]# dstbn[ 1]# l m vccp vss d[23]# d[21]# vss dstbp[ 1]# m n vccp d[16]# vss dinv[1]# d[31]# vss n p vss d[26]# d[25]# vss d[24]# d[18]# p r vccp vss d[19]# d[28]# vss comp[0 ] r t vccp d[37]# vss d[27]# d[30]# vss t u vss dinv[2]# d[39]# vss d[38]# comp[1 ] u v vccp vss d[36]# d[34]# vss d[35]# v w vccp d[41]# vss d[43]# d[44]# vss w y vss d[32]# d[42]# vss d[40]# dstbn[ 2]# y aa vss vcc vss vcc vcc vss vcc d[50]# vss d[45]# d[46]# vss dstbp[ 2]# a a ab vcc vcc vss vcc vcc vss vcc d[52]# d[51]# vss d[33]# d[47]# vss a b ac vss vcc vss vcc vcc vss dinv[3 ]# vss d[60]# d[63]# vss d[57]# d[53]# ac a d vcc vcc vss vcc vcc vss d[54]# d[59]# vss d[61]# d[49]# vss gtlref a d ae vss vcc vss vcc vcc vss vcc d[58]# d[55]# vss d[48]# dstbn[3] # vss ae af vcc vcc vss vcc vcc vss vcc vss d[62]# d[56]# dstbp[3] # vss test4 af 14 15 16 17 18 19 20 21 22 23 24 25 26
datasheet 41 package mechanical specifications and pin information table 15. sff processor top view upper left side bd bc bb ba ay aw av au at ar ap an am al ak aj ah ag af ae ad ac 1 vss vss tdo a[35]# a[17]# a[31]# a[30]# a[19]# comp[ 2] a[16]# 2 vss bpm[3] # preq# a[22]# a[34]# a[32]# a[21]# a[23]# comp[ 3] a[11]# 3 vss vss vss vss vss vss vss vss vss vss vss 4 vss vid[5] vid[6] tck a[20]# a[28]# a[27]# a[18]# a[26]# a[24]# a[12]# 5 vid[4] bpm[2] # tms a[33]# a[29]# adstb [1]# rsvd0 4 a[25]# rsvd0 3 a[14]# a[10]# 6 vss vss vss vss vss vss vss vss vss vss vss 7 vid[1] bpm[1] # tdi vss vccp vccp vccp vccp vccp vccp vccp 8 vid[0] vid[3] bpm[0] # trst# vss vss vss vss vss vss vss 9 vss vss vss vss vccp vccp vccp vccp vccp vccp vccp 10 psi# vid[2] test5 prdy# vss vccp vss vccp vss vccp vss 11 vss vss vss vccp vccp vccp vccp vccp vccp vccp vccp 12 vccs ense vss vss vss vss vccp vss vccp vss vccp vss 13 vssse nse vss vss vccp vccp vccp vccp vccp vccp vccp vccp 14 vcc vcc vcc vcc vcc vcc vcc vccp vccp vccp vccp 15 vss vss vss vss vss vss vss vss vss vss vss 16 vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc 17 vss vss vss vss vss vss vss vss vss vss vss 18 vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc 19 vss vss vss vss vss vss vss vss vss vss vss 20 vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc 21 vss vss vss vss vss vss vss vss vss vss vss 22 vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc
package mechanical specifications and pin information 42 datasheet table 16. sff processor top view upper right side ab aa y w v u t r p n m l k j h g f e d c b a 1 a[7]# a[5]# req[2] # req[0] # lock# trdy# dbsy# vss vss 2 a[15]# rsvd0 2 rsvd0 1 a[9]# a[3]# br0# rs[0]# hit# hitm# vss 3 vss vss vss vss vss vss vss vss vss vss 4 a[8]# adstb [0]# a[4]# a[6]# req[3] # ads# rs[2]# rs[1]# rsvd0 6 ferr# vss 5 a[13]# req[4] # vss req[1] # defer # bpri# bnr# reset # smi# lint1 vss 6 vss vss vss vss vss vss vss vss vss vss vss 7 vccp vccp vccp vccp vccp vccp dbr# dprst p# pwrg ood a20m# vss 8 vss vss vss vss vss vss vss rsvd0 7 stpcl k# init# dpslp # 9 vccp vccp vccp vccp vccp vccp rsvd0 5 vss vss lint0 vss 10 vccp vss vccp vss vccp vss vccp vss ignne # slp# ther mtrip # 11 vccp vccp vccp vccp vccp vccp vccp vccp vccp vss vss 12 vccp vss vccp vss vccp vss vccp vccp vccp vccp vccp 13 vccp vccp vccp vccp vccp vccp vccp vccp vccp vccp vccp 14 vccp vccp vccp vccp vccp vccp vccp vccp vccp vccp vccp 15 vss vss vss vss vss vss vss vss vss vss vss 16 vccvccvccvccvccvccvccvccvccvccvcc 17 vss vss vss vss vss vss vss vss vss vss vss 18 vccvccvccvccvccvccvccvccvccvccvcc 19 vss vss vss vss vss vss vss vss vss vss vss 20 vccvccvccvccvccvccvccvccvccvccvcc 21 vss vss vss vss vss vss vss vss vss vss vss 22 vccvccvccvccvccvccvccvccvccvccvcc
datasheet 43 package mechanical specifications and pin information table 17. sff processor top view lower left side bd bc bb ba ay aw av au at ar ap an am al ak aj ah ag af ae ad ac 23 vss vss vss vss vss vss vss vss vss vss vss 24 vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc 25 vss vss vss vss vss vss vss vss vss vss vss 26 vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc 27 vss vss vss vss vss vss vss vss vss vss vss 28 vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc 29 vss vss vss vss vss vss vss vss vss vss vss 30 vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc 31 vss vss vss vss vss vss vss vss vss vss vss 32 vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc 33 vss vss vss vcc vcc vcc vcc vcc vcc vcc vcc 34 thrm dc thrm da vss vss vcc vss vss vss vss vss vss 35 d[58]# d[62]# vss vss vss vccp vccp vccp vccp vccp vccp 36 vss vss d[56]# vss vss vccp vss vccp vss vccp vss 37 dinv[3 ]# d[54]# vss vss vss vccp vccp vccp vccp vccp vccp 38 vss d[55]# dstbp [3]# d[48]# vss vccp vss vccp vss vccp vss 39 d[59]# vss vss vss vss vss vss vss vss vss vss 40 vss d[61]# dstbn [3]# d[50]# d[57]# d[45]# d[42]# d[43]# d[34]# d[35]# d[26]# 41 vss d[60]# d[52]# d[51]# d[53]# d[46]# d[47]# dinv[2 ]# d[37]# test4 d[27]# 42 vss vss vss vss vss vss vss vss vss vss 43 vss gtlre f d[63]# d[33]# d[41]# dstbp [2]# d[36]# d[44]# comp[ 0] test6 44 vss vss d[49]# d[32]# d[40]# dstbn [2]# d[39]# d[38]# comp[ 1]
package mechanical specifications and pin information 44 datasheet table 18. sff processor top view lower right side ab aa y w v u t r p n m l k j h g f e d c b a 23 vss vss vss vss vss vss vss vss vss vss vss 24 vccvccvccvccvccvccvccvccvccvccvcc 25 vss vss vss vss vss vss vss vss vss vss vss 26 vccvccvccvccvccvccvccvccvccvccvcc 27 vss vss vss vss vss vss vss vss vss vss vss 28 vccvccvccvccvccvccvccvccvccvccvcc 29 vss vss vss vss vss vss vss vss vss vss vss 30 vccvccvccvccvccvccvccvccvccvccvcc 31 vss vss vss vss vss vss vss vss vss vss vss 32 vccvccvccvccvccvccvccvccvccvccpvccp 33 vcc vcc vcc vcc vcc vcc vcc vcc vccp vccp vccp 34 vss vss vss vss vss vss vss vss vccp vcca vcca 35 vccp vccp vccp vccp vccp vccp vccp vccp vccp bclk[ 1] bclk[ 0] 36 vccp vss vccp vss vccp vss vccp vccp vccp vss vss 37 vccp vccp vccp vccp vccp vccp vccp vss test1 bsel[1 ] bsel[0 ] 38 vccp vss vccp vss vccp vss vccp vss drdy# proc hot# bsel[2 ] 39 vss vss vss vss vss vss vss d[6]# vss vss vss 40 d[25]# d[29]# d[17]# d[11]# dinv[0 ]# d[12]# dstbn [0]# d[4]# d[0]# test2 ierr# 41 d[24]# d[21]# d[23]# d[20]# d[10]# d[8]# dstbp [0]# d[13]# d[7]# dpwr # vss 42 vss vss vss vss vss vss vss vss vss vss vss 43 d[28]# dstbp [1]# dstbn [1]# dinv[1 ]# d[22]# d[15]# d[3]# d[1]# d[2]# test3 44 d[19]# d[30]# d[18]# d[31]# d[16]# d[14]# d[9]# d[5]# vss vss
datasheet 45 package mechanical specifications and pin information table 19. pin listin g by pin name (sheet 1 of 16) pin name pin number signal buffer type direction a[3]# j4 source synch input/ output a[4]# l5 source synch input/ output a[5]# l4 source synch input/ output a[6]# k5 source synch input/ output a[7]# m3 source synch input/ output a[8]# n2 source synch input/ output a[9]# j1 source synch input/ output a[10]# n3 source synch input/ output a[11]# p5 source synch input/ output a[12]# p2 source synch input/ output a[13]# l2 source synch input/ output a[14]# p4 source synch input/ output a[15]# p1 source synch input/ output a[16]# r1 source synch input/ output a[17]# y2 source synch input/ output a[18]# u5 source synch input/ output a[19]# r3 source synch input/ output a[20]# w6 source synch input/ output a[21]# u4 source synch input/ output a[22]# y5 source synch input/ output a[23]# u1 source synch input/ output a[24]# r4 source synch input/ output a[25]# t5 source synch input/ output a[26]# t3 source synch input/ output a[27]# w2 source synch input/ output a[28]# w5 source synch input/ output a[29]# y4 source synch input/ output a[30]# u2 source synch input/ output a[31]# v4 source synch input/ output a[32]# w3 source synch input/ output a[33]# aa4 source synch input/ output a[34]# ab2 source synch input/ output a[35]# aa3 source synch input/ output a20m# a6 cmos input ads# h1 common clock input/ output adstb[0]# m1 source synch input/ output adstb[1]# v1 source synch input/ output bclk[0] a22 bus clock input bclk[1] a21 bus clock input bnr# e2 common clock input/ output bpm[0]# ad4 common clock input/ output bpm[1]# ad3 common clock output bpm[2]# ad1 common clock output bpm[3]# ac4 common clock input/ output bpri# g5 common clock input table 19. pin listing by pin name (sheet 2 of 16) pin name pin number signal buffer type direction
package mechanical specific ations and pi n information 46 datasheet br0# f1 common clock input/ output bsel[0] b22 cmos output bsel[1] b23 cmos output bsel[2] c21 cmos output comp[0] r26 power/other input/ output comp[1] u26 power/other input/ output comp[2] aa1 power/other input/ output comp[3] y1 power/other input/ output d[0]# e22 source synch input/ output d[1]# f24 source synch input/ output d[2]# e26 source synch input/ output d[3]# g22 source synch input/ output d[4]# f23 source synch input/ output d[5]# g25 source synch input/ output d[6]# e25 source synch input/ output d[7]# e23 source synch input/ output d[8]# k24 source synch input/ output d[9]# g24 source synch input/ output d[10]# j24 source synch input/ output d[11]# j23 source synch input/ output d[12]# h22 source synch input/ output d[13]# f26 source synch input/ output d[14]# k22 source synch input/ output table 19. pin listing by pin name (sheet 3 of 16) pin name pin number signal buffer type direction d[15]# h23 source synch input/ output d[16]# n22 source synch input/ output d[17]# k25 source synch input/ output d[18]# p26 source synch input/ output d[19]# r23 source synch input/ output d[20]# l23 source synch input/ output d[21]# m24 source synch input/ output d[22]# l22 source synch input/ output d[23]# m23 source synch input/ output d[24]# p25 source synch input/ output d[25]# p23 source synch input/ output d[26]# p22 source synch input/ output d[27]# t24 source synch input/ output d[28]# r24 source synch input/ output d[29]# l25 source synch input/ output d[30]# t25 source synch input/ output d[31]# n25 source synch input/ output d[32]# y22 source synch input/ output d[33]# ab24 source synch input/ output d[34]# v24 source synch input/ output d[35]# v26 source synch input/ output d[36]# v23 source synch input/ output table 19. pin listing by pin name (sheet 4 of 16) pin name pin number signal buffer type direction
datasheet 47 package mechanical specifications and pin information d[37]# t22 source synch input/ output d[38]# u25 source synch input/ output d[39]# u23 source synch input/ output d[40]# y25 source synch input/ output d[41]# w22 source synch input/ output d[42]# y23 source synch input/ output d[43]# w24 source synch input/ output d[44]# w25 source synch input/ output d[45]# aa23 source synch input/ output d[46]# aa24 source synch input/ output d[47]# ab25 source synch input/ output d[48]# ae24 source synch input/ output d[49]# ad24 source synch input/ output d[50]# aa21 source synch input/ output d[51]# ab22 source synch input/ output d[52]# ab21 source synch input/ output d[53]# ac26 source synch input/ output d[54]# ad20 source synch input/ output d[55]# ae22 source synch input/ output d[56]# af23 source synch input/ output d[57]# ac25 source synch input/ output d[58]# ae21 source synch input/ output table 19. pin listin g by pin name (sheet 5 of 16) pin name pin number signal buffer type direction d[59]# ad21 source synch input/ output d[60]# ac22 source synch input/ output d[61]# ad23 source synch input/ output d[62]# af22 source synch input/ output d[63]# ac23 source synch input/ output dbr# c20 cmos output dbsy# e1 common clock input/ output defer# h5 common clock input dinv[0]# h25 source synch input/ output dinv[1]# n24 source synch input/ output dinv[2]# u22 source synch input/ output dinv[3]# ac20 source synch input/ output dprstp# e5 cmos input dpslp# b5 cmos input dpwr# d24 common clock input/ output drdy# f21 common clock input/ output dstbn[0]# j26 source synch input/ output dstbn[1]# l26 source synch input/ output dstbn[2]# y26 source synch input/ output dstbn[3]# ae25 source synch input/ output dstbp[0]# h26 source synch input/ output dstbp[1]# m26 source synch input/ output dstbp[2]# aa26 source synch input/ output table 19. pin listing by pin name (sheet 6 of 16) pin name pin number signal buffer type direction
package mechanical specific ations and pi n information 48 datasheet dstbp[3]# af24 source synch input/ output ferr# a5 open drain output gtlref ad26 power/other input hit# g6 common clock input/ output hitm# e4 common clock input/ output ierr# d20 open drain output ignne# c4 cmos input init# b3 cmos input lint0 c6 cmos input lint1 b4 cmos input lock# h4 common clock input/ output prdy# ac2 common clock output preq# ac1 common clock input prochot# d21 open drain input/ output psi# ae6 cmos output pwrgood d6 cmos input req[0]# k3 source synch input/ output req[1]# h2 source synch input/ output req[2]# k2 source synch input/ output req[3]# j3 source synch input/ output req[4]# l1 source synch input/ output reset# c1 common clock input rs[0]# f3 common clock input rs[1]# f4 common clock input rs[2]# g3 common clock input rsvd b2 reserved rsvd c3 reserved rsvd d2 reserved rsvd d3 reserved rsvd d22 reserved table 19. pin listing by pin name (sheet 7 of 16) pin name pin number signal buffer type direction rsvd f6 reserved rsvd m4 reserved rsvd n5 reserved rsvd t2 reserved rsvd v3 reserved slp# d7 cmos input smi# a3 cmos input stpclk# d5 cmos input tck ac5 cmos input tdi aa6 cmos input tdo ab3 open drain output test1 c23 test test2 d25 test test3 c24 test test4 af26 test test5 af1 test test6 a26 test thermtrip # c7 open drain output thrmda a24 power/other thrmdc b25 power/other tms ab5 cmos input trdy# g2 common clock input trst# ab6 cmos input vcc a7 power/other vcc a9 power/other vcc a10 power/other vcc a12 power/other vcc a13 power/other vcc a15 power/other vcc a17 power/other vcc a18 power/other vcc a20 power/other vcc aa7 power/other vcc aa9 power/other vcc aa10 power/other vcc aa12 power/other table 19. pin listing by pin name (sheet 8 of 16) pin name pin number signal buffer type direction
datasheet 49 package mechanical specifications and pin information vcc aa13 power/other vcc aa15 power/other vcc aa17 power/other vcc aa18 power/other vcc aa20 power/other vcc ab7 power/other vcc ab9 power/other vcc ab10 power/other vcc ab12 power/other vcc ab14 power/other vcc ab15 power/other vcc ab17 power/other vcc ab18 power/other vcc ab20 power/other vcc ac7 power/other vcc ac9 power/other vcc ac10 power/other vcc ac12 power/other vcc ac13 power/other vcc ac15 power/other vcc ac17 power/other vcc ac18 power/other vcc ad7 power/other vcc ad9 power/other vcc ad10 power/other vcc ad12 power/other vcc ad14 power/other vcc ad15 power/other vcc ad17 power/other vcc ad18 power/other vcc ae9 power/other vcc ae10 power/other vcc ae12 power/other vcc ae13 power/other vcc ae15 power/other vcc ae17 power/other table 19. pin listin g by pin name (sheet 9 of 16) pin name pin number signal buffer type direction vcc ae18 power/other vcc ae20 power/other vcc af9 power/other vcc af10 power/other vcc af12 power/other vcc af14 power/other vcc af15 power/other vcc af17 power/other vcc af18 power/other vcc af20 power/other vcc b7 power/other vcc b9 power/other vcc b10 power/other vcc b12 power/other vcc b14 power/other vcc b15 power/other vcc b17 power/other vcc b18 power/other vcc b20 power/other vcc c9 power/other vcc c10 power/other vcc c12 power/other vcc c13 power/other vcc c15 power/other vcc c17 power/other vcc c18 power/other vcc d9 power/other vcc d10 power/other vcc d12 power/other vcc d14 power/other vcc d15 power/other vcc d17 power/other vcc d18 power/other vcc e7 power/other vcc e9 power/other vcc e10 power/other table 19. pin listing by pin name (sheet 10 of 16) pin name pin number signal buffer type direction
package mechanical specific ations and pi n information 50 datasheet vcc e12 power/other vcc e13 power/other vcc e15 power/other vcc e17 power/other vcc e18 power/other vcc e20 power/other vcc f7 power/other vcc f9 power/other vcc f10 power/other vcc f12 power/other vcc f14 power/other vcc f15 power/other vcc f17 power/other vcc f18 power/other vcc f20 power/other vcca b26 power/other vcca c26 power/other vccp g21 power/other vccp j6 power/other vccp j21 power/other vccp k6 power/other vccp k21 power/other vccp m6 power/other vccp m21 power/other vccp n6 power/other vccp n21 power/other vccp r6 power/other vccp r21 power/other vccp t6 power/other vccp t21 power/other vccp v6 power/other vccp v21 power/other vccp w21 power/other vccsense af7 power/other vid[0] ad6 cmos output vid[1] af5 cmos output table 19. pin listing by pin name (sheet 11 of 16) pin name pin number signal buffer type direction vid[2] ae5 cmos output vid[3] af4 cmos output vid[4] ae3 cmos output vid[5] af3 cmos output vid[6] ae2 cmos output vss a2 power/other vss a4 power/other vss a8 power/other vss a11 power/other vss a14 power/other vss a16 power/other vss a19 power/other vss a23 power/other vss a25 power/other vss aa2 power/other vss aa5 power/other vss aa8 power/other vss aa11 power/other vss aa14 power/other vss aa16 power/other vss aa19 power/other vss aa22 power/other vss aa25 power/other vss ab1 power/other vss ab4 power/other vss ab8 power/other vss ab11 power/other vss ab13 power/other vss ab16 power/other vss ab19 power/other vss ab23 power/other vss ab26 power/other vss ac3 power/other vss ac6 power/other vss ac8 power/other vss ac11 power/other table 19. pin listing by pin name (sheet 12 of 16) pin name pin number signal buffer type direction
datasheet 51 package mechanical specifications and pin information vss ac14 power/other vss ac16 power/other vss ac19 power/other vss ac21 power/other vss ac24 power/other vss ad2 power/other vss ad5 power/other vss ad8 power/other vss ad11 power/other vss ad13 power/other vss ad16 power/other vss ad19 power/other vss ad22 power/other vss ad25 power/other vss ae1 power/other vss ae4 power/other vss ae8 power/other vss ae11 power/other vss ae14 power/other vss ae16 power/other vss ae19 power/other vss ae23 power/other vss ae26 power/other vss af2 power/other vss af6 power/other vss af8 power/other vss af11 power/other vss af13 power/other vss af16 power/other vss af19 power/other vss af21 power/other vss af25 power/other vss b6 power/other vss b8 power/other vss b11 power/other vss b13 power/other table 19. pin listin g by pin name (sheet 13 of 16) pin name pin number signal buffer type direction vss b16 power/other vss b19 power/other vss b21 power/other vss b24 power/other vss c2 power/other vss c5 power/other vss c8 power/other vss c11 power/other vss c14 power/other vss c16 power/other vss c19 power/other vss c22 power/other vss c25 power/other vss d1 power/other vss d4 power/other vss d8 power/other vss d11 power/other vss d13 power/other vss d16 power/other vss d19 power/other vss d23 power/other vss d26 power/other vss e3 power/other vss e6 power/other vss e8 power/other vss e11 power/other vss e14 power/other vss e16 power/other vss e19 power/other vss e21 power/other vss e24 power/other vss f2 power/other vss f5 power/other vss f8 power/other vss f11 power/other vss f13 power/other table 19. pin listing by pin name (sheet 14 of 16) pin name pin number signal buffer type direction
package mechanical specific ations and pi n information 52 datasheet vss f16 power/other vss f19 power/other vss f22 power/other vss f25 power/other vss g1 power/other vss g4 power/other vss g23 power/other vss g26 power/other vss h3 power/other vss h6 power/other vss h21 power/other vss h24 power/other vss j2 power/other vss j5 power/other vss j22 power/other vss j25 power/other vss k1 power/other vss k4 power/other vss k23 power/other vss k26 power/other vss l3 power/other vss l6 power/other vss l21 power/other vss l24 power/other vss m2 power/other vss m5 power/other vss m22 power/other vss m25 power/other vss n1 power/other vss n4 power/other vss n23 power/other vss n26 power/other vss p3 power/other vss p6 power/other vss p21 power/other vss p24 power/other table 19. pin listing by pin name (sheet 15 of 16) pin name pin number signal buffer type direction vss r2 power/other vss r5 power/other vss r22 power/other vss r25 power/other vss t1 power/other vss t4 power/other vss t23 power/other vss t26 power/other vss u3 power/other vss u6 power/other vss u21 power/other vss u24 power/other vss v2 power/other vss v5 power/other vss v22 power/other vss v25 power/other vss w1 power/other vss w4 power/other vss w23 power/other vss w26 power/other vss y3 power/other vss y6 power/other vss y21 power/other vss y24 power/other vsssense ae7 power/other output table 20. pin listing by pin number (sheet 1 of 17) pin name pin number signal buffer type direction vss a2 power/other smi# a3 cmos input vss a4 power/other ferr# a5 open drain output a20m# a6 cmos input vcc a7 power/other table 19. pin listing by pin name (sheet 16 of 16) pin name pin number signal buffer type direction
datasheet 53 package mechanical specifications and pin information vss a8 power/other vcc a9 power/other vcc a10 power/other vss a11 power/other vcc a12 power/other vcc a13 power/other vss a14 power/other vcc a15 power/other vss a16 power/other vcc a17 power/other vcc a18 power/other vss a19 power/other vcc a20 power/other bclk[1] a21 bus clock input bclk[0] a22 bus clock input vss a23 power/other thrmda a24 power/other vss a25 power/other test6 a26 test comp[2] aa1 power/other input/ output vss aa2 power/other a[35]# aa3 source synch input/ output a[33]# aa4 source synch input/ output vss aa5 power/other tdi aa6 cmos input vcc aa7 power/other vss aa8 power/other vcc aa9 power/other vcc aa10 power/other vss aa11 power/other vcc aa12 power/other vcc aa13 power/other vss aa14 power/other vcc aa15 power/other table 20. pin listing by pin number (sheet 2 of 17) pin name pin number signal buffer type direction vss aa16 power/other vcc aa17 power/other vcc aa18 power/other vss aa19 power/other vcc aa20 power/other d[50]# aa21 source synch input/ output vss aa22 power/other d[45]# aa23 source synch input/ output d[46]# aa24 source synch input/ output vss aa25 power/other dstbp[2]# aa26 source synch input/ output vss ab1 power/other a[34]# ab2 source synch input/ output tdo ab3 open drain output vss ab4 power/other tms ab5 cmos input trst# ab6 cmos input vcc ab7 power/other vss ab8 power/other vcc ab9 power/other vcc ab10 power/other vss ab11 power/other vcc ab12 power/other vss ab13 power/other vcc ab14 power/other vcc ab15 power/other vss ab16 power/other vcc ab17 power/other vcc ab18 power/other vss ab19 power/other vcc ab20 power/other d[52]# ab21 source synch input/ output table 20. pin listing by pin number (sheet 3 of 17) pin name pin number signal buffer type direction
package mechanical specific ations and pi n information 54 datasheet d[51]# ab22 source synch input/ output vss ab23 power/other d[33]# ab24 source synch input/ output d[47]# ab25 source synch input/ output vss ab26 power/other preq# ac1 common clock input prdy# ac2 common clock output vss ac3 power/other bpm[3]# ac4 common clock input/ output tck ac5 cmos input vss ac6 power/other vcc ac7 power/other vss ac8 power/other vcc ac9 power/other vcc ac10 power/other vss ac11 power/other vcc ac12 power/other vcc ac13 power/other vss ac14 power/other vcc ac15 power/other vss ac16 power/other vcc ac17 power/other vcc ac18 power/other vss ac19 power/other dinv[3]# ac20 source synch input/ output vss ac21 power/other d[60]# ac22 source synch input/ output d[63]# ac23 source synch input/ output vss ac24 power/other d[57]# ac25 source synch input/ output table 20. pin listin g by pin number (sheet 4 of 17) pin name pin number signal buffer type direction d[53]# ac26 source synch input/ output bpm[2]# ad1 common clock output vss ad2 power/other bpm[1]# ad3 common clock output bpm[0]# ad4 common clock input/ output vss ad5 power/other vid[0] ad6 cmos output vcc ad7 power/other vss ad8 power/other vcc ad9 power/other vcc ad10 power/other vss ad11 power/other vcc ad12 power/other vss ad13 power/other vcc ad14 power/other vcc ad15 power/other vss ad16 power/other vcc ad17 power/other vcc ad18 power/other vss ad19 power/other d[54]# ad20 source synch input/ output d[59]# ad21 source synch input/ output vss ad22 power/other d[61]# ad23 source synch input/ output d[49]# ad24 source synch input/ output vss ad25 power/other gtlref ad26 power/other input vss ae1 power/other vid[6] ae2 cmos output vid[4] ae3 cmos output vss ae4 power/other table 20. pin listing by pin number (sheet 5 of 17) pin name pin number signal buffer type direction
datasheet 55 package mechanical specifications and pin information vid[2] ae5 cmos output psi# ae6 cmos output vsssense ae7 power/other output vss ae8 power/other vcc ae9 power/other vcc ae10 power/other vss ae11 power/other vcc ae12 power/other vcc ae13 power/other vss ae14 power/other vcc ae15 power/other vss ae16 power/other vcc ae17 power/other vcc ae18 power/other vss ae19 power/other vcc ae20 power/other d[58]# ae21 source synch input/ output d[55]# ae22 source synch input/ output vss ae23 power/other d[48]# ae24 source synch input/ output dstbn[3]# ae25 source synch input/ output vss ae26 power/other test5 af1 test vss af2 power/other vid[5] af3 cmos output vid[3] af4 cmos output vid[1] af5 cmos output vss af6 power/other vccsense af7 power/other vss af8 power/other vcc af9 power/other vcc af10 power/other vss af11 power/other vcc af12 power/other table 20. pin listing by pin number (sheet 6 of 17) pin name pin number signal buffer type direction vss af13 power/other vcc af14 power/other vcc af15 power/other vss af16 power/other vcc af17 power/other vcc af18 power/other vss af19 power/other vcc af20 power/other vss af21 power/other d[62]# af22 source synch input/ output d[56]# af23 source synch input/ output dstbp[3]# af24 source synch input/ output vss af25 power/other test4 af26 test rsvd b2 reserved init# b3 cmos input lint1 b4 cmos input dpslp# b5 cmos input vss b6 power/other vcc b7 power/other vss b8 power/other vcc b9 power/other vcc b10 power/other vss b11 power/other vcc b12 power/other vss b13 power/other vcc b14 power/other vcc b15 power/other vss b16 power/other vcc b17 power/other vcc b18 power/other vss b19 power/other vcc b20 power/other vss b21 power/other table 20. pin listing by pin number (sheet 7 of 17) pin name pin number signal buffer type direction
package mechanical specific ations and pi n information 56 datasheet bsel[0] b22 cmos output bsel[1] b23 cmos output vss b24 power/other thrmdc b25 power/other vcca b26 power/other reset# c1 common clock input vss c2 power/other rsvd c3 reserved ignne# c4 cmos input vss c5 power/other lint0 c6 cmos input thermtrip # c7 open drain output vss c8 power/other vcc c9 power/other vcc c10 power/other vss c11 power/other vcc c12 power/other vcc c13 power/other vss c14 power/other vcc c15 power/other vss c16 power/other vcc c17 power/other vcc c18 power/other vss c19 power/other dbr# c20 cmos output bsel[2] c21 cmos output vss c22 power/other test1 c23 test test3 c24 test vss c25 power/other vcca c26 power/other vss d1 power/other rsvd d2 reserved rsvd d3 reserved vss d4 power/other table 20. pin listin g by pin number (sheet 8 of 17) pin name pin number signal buffer type direction stpclk# d5 cmos input pwrgood d6 cmos input slp# d7 cmos input vss d8 power/other vcc d9 power/other vcc d10 power/other vss d11 power/other vcc d12 power/other vss d13 power/other vcc d14 power/other vcc d15 power/other vss d16 power/other vcc d17 power/other vcc d18 power/other vss d19 power/other ierr# d20 open drain output prochot# d21 open drain input/ output rsvd d22 reserved vss d23 power/other dpwr# d24 common clock input/ output test2 d25 test vss d26 power/other dbsy# e1 common clock input/ output bnr# e2 common clock input/ output vss e3 power/other hitm# e4 common clock input/ output dprstp# e5 cmos input vss e6 power/other vcc e7 power/other vss e8 power/other vcc e9 power/other vcc e10 power/other vss e11 power/other table 20. pin listing by pin number (sheet 9 of 17) pin name pin number signal buffer type direction
datasheet 57 package mechanical specifications and pin information vcc e12 power/other vcc e13 power/other vss e14 power/other vcc e15 power/other vss e16 power/other vcc e17 power/other vcc e18 power/other vss e19 power/other vcc e20 power/other vss e21 power/other d[0]# e22 source synch input/ output d[7]# e23 source synch input/ output vss e24 power/other d[6]# e25 source synch input/ output d[2]# e26 source synch input/ output br0# f1 common clock input/ output vss f2 power/other rs[0]# f3 common clock input rs[1]# f4 common clock input vss f5 power/other rsvd f6 reserved vcc f7 power/other vss f8 power/other vcc f9 power/other vcc f10 power/other vss f11 power/other vcc f12 power/other vss f13 power/other vcc f14 power/other vcc f15 power/other vss f16 power/other vcc f17 power/other table 20. pin listing by pin number (sheet 10 of 17) pin name pin number signal buffer type direction vcc f18 power/other vss f19 power/other vcc f20 power/other drdy# f21 common clock input/ output vss f22 power/other d[4]# f23 source synch input/ output d[1]# f24 source synch input/ output vss f25 power/other d[13]# f26 source synch input/ output vss g1 power/other trdy# g2 common clock input rs[2]# g3 common clock input vss g4 power/other bpri# g5 common clock input hit# g6 common clock input/ output vccp g21 power/other d[3]# g22 source synch input/ output vss g23 power/other d[9]# g24 source synch input/ output d[5]# g25 source synch input/ output vss g26 power/other ads# h1 common clock input/ output req[1]# h2 source synch input/ output vss h3 power/other lock# h4 common clock input/ output defer# h5 common clock input table 20. pin listing by pin number (sheet 11 of 17) pin name pin number signal buffer type direction
package mechanical specific ations and pi n information 58 datasheet vss h6 power/other vss h21 power/other d[12]# h22 source synch input/ output d[15]# h23 source synch input/ output vss h24 power/other dinv[0]# h25 source synch input/ output dstbp[0]# h26 source synch input/ output a[9]# j1 source synch input/ output vss j2 power/other req[3]# j3 source synch input/ output a[3]# j4 source synch input/ output vss j5 power/other vccp j6 power/other vccp j21 power/other vss j22 power/other d[11]# j23 source synch input/ output d[10]# j24 source synch input/ output vss j25 power/other dstbn[0]# j26 source synch input/ output vss k1 power/other req[2]# k2 source synch input/ output req[0]# k3 source synch input/ output vss k4 power/other a[6]# k5 source synch input/ output vccp k6 power/other vccp k21 power/other d[14]# k22 source synch input/ output table 20. pin listin g by pin number (sheet 12 of 17) pin name pin number signal buffer type direction vss k23 power/other d[8]# k24 source synch input/ output d[17]# k25 source synch input/ output vss k26 power/other req[4]# l1 source synch input/ output a[13]# l2 source synch input/ output vss l3 power/other a[5]# l4 source synch input/ output a[4]# l5 source synch input/ output vss l6 power/other vss l21 power/other d[22]# l22 source synch input/ output d[20]# l23 source synch input/ output vss l24 power/other d[29]# l25 source synch input/ output dstbn[1]# l26 source synch input/ output adstb[0]# m1 source synch input/ output vss m2 power/other a[7]# m3 source synch input/ output rsvd m4 reserved vss m5 power/other vccp m6 power/other vccp m21 power/other vss m22 power/other d[23]# m23 source synch input/ output d[21]# m24 source synch input/ output vss m25 power/other table 20. pin listing by pin number (sheet 13 of 17) pin name pin number signal buffer type direction
datasheet 59 package mechanical specifications and pin information dstbp[1]# m26 source synch input/ output vss n1 power/other a[8]# n2 source synch input/ output a[10]# n3 source synch input/ output vss n4 power/other rsvd n5 reserved vccp n6 power/other vccp n21 power/other d[16]# n22 source synch input/ output vss n23 power/other dinv[1]# n24 source synch input/ output d[31]# n25 source synch input/ output vss n26 power/other a[15]# p1 source synch input/ output a[12]# p2 source synch input/ output vss p3 power/other a[14]# p4 source synch input/ output a[11]# p5 source synch input/ output vss p6 power/other vss p21 power/other d[26]# p22 source synch input/ output d[25]# p23 source synch input/ output vss p24 power/other d[24]# p25 source synch input/ output d[18]# p26 source synch input/ output a[16]# r1 source synch input/ output table 20. pin listing by pin number (sheet 14 of 17) pin name pin number signal buffer type direction vss r2 power/other a[19]# r3 source synch input/ output a[24]# r4 source synch input/ output vss r5 power/other vccp r6 power/other vccp r21 power/other vss r22 power/other d[19]# r23 source synch input/ output d[28]# r24 source synch input/ output vss r25 power/other comp[0] r26 power/other input/ output vss t1 power/other rsvd t2 reserved a[26]# t3 source synch input/ output vss t4 power/other a[25]# t5 source synch input/ output vccp t6 power/other vccp t21 power/other d[37]# t22 source synch input/ output vss t23 power/other d[27]# t24 source synch input/ output d[30]# t25 source synch input/ output vss t26 power/other a[23]# u1 source synch input/ output a[30]# u2 source synch input/ output vss u3 power/other a[21]# u4 source synch input/ output table 20. pin listing by pin number (sheet 15 of 17) pin name pin number signal buffer type direction
package mechanical specific ations and pi n information 60 datasheet a[18]# u5 source synch input/ output vss u6 power/other vss u21 power/other dinv[2]# u22 source synch input/ output d[39]# u23 source synch input/ output vss u24 power/other d[38]# u25 source synch input/ output comp[1] u26 power/other input/ output adstb[1]# v1 source synch input/ output vss v2 power/other rsvd v3 reserved a[31]# v4 source synch input/ output vss v5 power/other vccp v6 power/other vccp v21 power/other vss v22 power/other d[36]# v23 source synch input/ output d[34]# v24 source synch input/ output vss v25 power/other d[35]# v26 source synch input/ output vss w1 power/other a[27]# w2 source synch input/ output a[32]# w3 source synch input/ output vss w4 power/other a[28]# w5 source synch input/ output a[20]# w6 source synch input/ output vccp w21 power/other table 20. pin listin g by pin number (sheet 16 of 17) pin name pin number signal buffer type direction d[41]# w22 source synch input/ output vss w23 power/other d[43]# w24 source synch input/ output d[44]# w25 source synch input/ output vss w26 power/other comp[3] y1 power/other input/ output a[17]# y2 source synch input/ output vss y3 power/other a[29]# y4 source synch input/ output a[22]# y5 source synch input/ output vss y6 power/other vss y21 power/other d[32]# y22 source synch input/ output d[42]# y23 source synch input/ output vss y24 power/other d[40]# y25 source synch input/ output dstbn[2]# y26 source synch input/ output table 20. pin listing by pin number (sheet 17 of 17) pin name pin number signal buffer type direction
datasheet 61 package mechanical specifications and pin information table 21. sff listing by ball name signal name ball number a[3]# p2 a[4]# v4 a[5]# w1 a[6]# t4 a[7]# aa1 a[8]# ab4 a[9]# t2 a[10]# ac5 a[11]# ad2 a[12]# ad4 a[13]# aa5 a[14]# ae5 a[15]# ab2 a[16]# ac1 a[17]# an1 a[18]# ak4 a[19]# ag1 a[20]# at4 a[21]# ak2 a[22]# at2 a[23]# ah2 a[24]# af4 a[25]# aj5 a[26]# ah4 a[27]# am4 a[28]# ap4 a[29]# ar5 a[30]# aj1 a[31]# al1 a[32]# am2 a[33]# au5 a[34]# ap2 a[35]# ar1 a20m# c7 ads# m4 adstb[0]# y4 adstb[1]# an5 bclk[0] a35 bclk[1] c35 bnr# j5 bpm[0]# ay8 bpm[1]# ba7 bpm[2]# ba5 bpm[3]# ay2 bpri# l5 br0# m2 bsel[0] a37 bsel[1] c37 bsel[2] b38 comp[0] ae43 comp[1] ad44 comp[2] ae1 comp[3] af2 d[0]# f40 d[1]# g43 d[2]# e43 d[3]# j43 d[4]# h40 d[5]# h44 d[6]# g39 d[7]# e41 d[8]# l41 d[9]# k44 d[10]# n41 d[11]# t40 d[12]# m40 d[13]# g41 d[14]# m44 d[15]# l43 d[16]# p44 d[17]# v40 d[18]# v44 d[19]# ab44 signal name ball number
package mechanical specific ations and pi n information 62 datasheet d[20]# r41 d[21]# w41 d[22]# n43 d[23]# u41 d[24]# aa41 d[25]# ab40 d[26]# ad40 d[27]# ac41 d[28]# aa43 d[29]# y40 d[30]# y44 d[31]# t44 d[32]# ap44 d[33]# ar43 d[34]# ah40 d[35]# af40 d[36]# aj43 d[37]# ag41 d[38]# af44 d[39]# ah44 d[40]# am44 d[41]# an43 d[42]# am40 d[43]# ak40 d[44]# ag43 d[45]# ap40 d[46]# an41 d[47]# al41 d[48]# av38 d[49]# at44 d[50]# av40 d[51]# au41 d[52]# aw41 d[53]# ar41 d[54]# ba37 d[55]# bb38 d[56]# ay36 d[57]# at40 signal name ball number d[58]# bc35 d[59]# bc39 d[60]# ba41 d[61]# bb40 d[62]# ba35 d[63]# au43 dbr# j7 dbsy# j1 defer# n5 dinv[0]# p40 dinv[1]# r43 dinv[2]# aj41 dinv[3]# bc37 dprstp# g7 dpslp# b8 dpwr# c41 drdy# f38 dstbn[0]# k40 dstbn[1]# u43 dstbn[2]# ak44 dstbn[3]# ay40 dstbp[0]# j41 dstbp[1]# w43 dstbp[2]# al43 dstbp[3]# ay38 ferr# d4 gtlref aw43 hit# h2 hitm# f2 ierr# b40 ignne# f10 init# d8 lint0 c9 lint1 c5 lock# n1 prdy# av10 preq# av2 prochot# d38 signal name ball number
datasheet 63 package mechanical specifications and pin information psi# bd10 pwrgood e7 req[0]# r1 req[1]# r5 req[2]# u1 req[3]# p4 req[4]# w5 reset# g5 rs[0]# k2 rs[1]# h4 rs[2]# k4 rsvd01 v2 rsvd02 y2 rsvd03 ag5 rsvd04 al5 rsvd05 j9 rsvd06 f4 rsvd07 h8 slp# d10 smi# e5 stpclk# f8 tck av4 tdi aw7 tdo au1 test1 e37 test2 d40 test3 c43 test4 ae41 test5 ay10 test6 ac43 thermtrip# b10 thrmda bb34 thrmdc bd34 tms aw5 trdy# l1 trst# av8 vcc aa33 vcc ab16 signal name ball number vcc ab18 vcc ab20 vcc ab22 vcc ab24 vcc ab26 vcc ab28 vcc ab30 vcc ab32 vcc ac33 vcc ad16 vcc ad18 vcc ad20 vcc ad22 vcc ad24 vcc ad26 vcc ad28 vcc ad30 vcc ad32 vcc ae33 vcc af16 vcc af18 vcc af20 vcc af22 vcc af24 vcc af26 vcc af28 vcc af30 vcc af32 vcc ag33 vcc ah16 vcc ah18 vcc ah20 vcc ah22 vcc ah24 vcc ah26 vcc ah28 vcc ah30 vcc ah32 signal name ball number
package mechanical specific ations and pi n information 64 datasheet vcc aj33 vcc ak16 vcc ak18 vcc ak20 vcc ak22 vcc ak24 vcc ak26 vcc ak28 vcc ak30 vcc ak32 vcc al33 vcc am14 vcc am16 vcc am18 vcc am20 vcc am22 vcc am24 vcc am26 vcc am28 vcc am30 vcc am32 vcc an33 vcc ap14 vcc ap16 vcc ap18 vcc ap20 vcc ap22 vcc ap24 vcc ap26 vcc ap28 vcc ap30 vcc ap32 vcc ar33 vcc at14 vcc at16 vcc at18 vcc at20 vcc at22 signal name ball number vcc at24 vcc at26 vcc at28 vcc at30 vcc at32 vcc at34 vcc au33 vcc av14 vcc av16 vcc av18 vcc av20 vcc av22 vcc av24 vcc av26 vcc av28 vcc av30 vcc av32 vcc ay14 vcc ay16 vcc ay18 vcc ay20 vcc ay22 vcc ay24 vcc ay26 vcc ay28 vcc ay30 vcc ay32 vcc b16 vcc b18 vcc b20 vcc b22 vcc b24 vcc b26 vcc b28 vcc b30 vcc bb14 vcc bb16 vcc bb18 signal name ball number
datasheet 65 package mechanical specifications and pin information vcc bb20 vcc bb22 vcc bb24 vcc bb26 vcc bb28 vcc bb30 vcc bb32 vcc bd14 vcc bd16 vcc bd18 vcc bd20 vcc bd22 vcc bd24 vcc bd26 vcc bd28 vcc bd30 vcc bd32 vcc d16 vcc d18 vcc d20 vcc d22 vcc d24 vcc d26 vcc d28 vcc d30 vcc f16 vcc f18 vcc f20 vcc f22 vcc f24 vcc f26 vcc f28 vcc f30 vcc f32 vcc g33 vcc h16 vcc h18 vcc h20 signal name ball number vcc h22 vcc h24 vcc h26 vcc h28 vcc h30 vcc h32 vcc j33 vcc k16 vcc k18 vcc k20 vcc k22 vcc k24 vcc k26 vcc k28 vcc k30 vcc k32 vcc l33 vcc m16 vcc m18 vcc m20 vcc m22 vcc m24 vcc m26 vcc m28 vcc m30 vcc m32 vcc n33 vcc p16 vcc p18 vcc p20 vcc p22 vcc p24 vcc p26 vcc p28 vcc p30 vcc p32 vcc r33 vcc t16 signal name ball number
package mechanical specific ations and pi n information 66 datasheet vcc t18 vcc t20 vcc t22 vcc t24 vcc t26 vcc t28 vcc t30 vcc t32 vcc u33 vcc v16 vcc v18 vcc v20 vcc v22 vcc v24 vcc v26 vcc v28 vcc v30 vcc v32 vcc w33 vcc y16 vcc y18 vcc y20 vcc y22 vcc y24 vcc y26 vcc y28 vcc y30 vcc y32 vcca b34 vcca d34 vccp a13 vccp a33 vccp aa7 vccp aa9 vccp aa11 vccp aa13 vccp aa35 vccp aa37 signal name ball number vccp ab10 vccp ab12 vccp ab14 vccp ab36 vccp ab38 vccp ac7 vccp ac9 vccp ac11 vccp ac13 vccp ac35 vccp ac37 vccp ad14 vccp ae7 vccp ae9 vccp ae11 vccp ae13 vccp ae35 vccp ae37 vccp af10 vccp af12 vccp af14 vccp af36 vccp af38 vccp ag7 vccp ag9 vccp ag11 vccp ag13 vccp ag35 vccp ag37 vccp ah14 vccp aj7 vccp aj9 vccp aj11 vccp aj13 vccp aj35 vccp aj37 vccp ak10 vccp ak12 signal name ball number
datasheet 67 package mechanical specifications and pin information vccp ak14 vccp ak36 vccp ak38 vccp al7 vccp al9 vccp al11 vccp al13 vccp al35 vccp al37 vccp an7 vccp an9 vccp an11 vccp an13 vccp an35 vccp an37 vccp ap10 vccp ap12 vccp ap36 vccp ap38 vccp ar7 vccp ar9 vccp ar11 vccp ar13 vccp au11 vccp au13 vccp b12 vccp b14 vccp b32 vccp c13 vccp c33 vccp d12 vccp d14 vccp d32 vccp e11 vccp e13 vccp e33 vccp e35 vccp f12 signal name ball number vccp f14 vccp f34 vccp f36 vccp g11 vccp g13 vccp g35 vccp h12 vccp h14 vccp h36 vccp j11 vccp j13 vccp j35 vccp j37 vccp k10 vccp k12 vccp k14 vccp k36 vccp k38 vccp l7 vccp l9 vccp l11 vccp l13 vccp l35 vccp l37 vccp m14 vccp n7 vccp n9 vccp n11 vccp n13 vccp n35 vccp n37 vccp p10 vccp p12 vccp p14 vccp p36 vccp p38 vccp r7 vccp r9 signal name ball number
package mechanical specific ations and pi n information 68 datasheet vccp r11 vccp r13 vccp r35 vccp r37 vccp t14 vccp u7 vccp u9 vccp u11 vccp u13 vccp u35 vccp u37 vccp v10 vccp v12 vccp v14 vccp v36 vccp v38 vccp w7 vccp w9 vccp w11 vccp w13 vccp w35 vccp w37 vccp y14 vccsense bd12 vid[0] bd8 vid[1] bc7 vid[2] bb10 vid[3] bb8 vid[4] bc5 vid[5] bb4 vid[6] ay4 vss a5 vss a7 vss a9 vss a11 vss a15 vss a17 vss a19 signal name ball number vss a21 vss a23 vss a25 vss a27 vss a29 vss a31 vss a39 vss a41 vss aa3 vss aa15 vss aa17 vss aa19 vss aa21 vss aa23 vss aa25 vss aa27 vss aa29 vss aa31 vss aa39 vss ab6 vss ab8 vss ab34 vss ab42 vss ac3 vss ac15 vss ac17 vss ac19 vss ac21 vss ac23 vss ac25 vss ac27 vss ac29 vss ac31 vss ac39 vss ad6 vss ad8 vss ad10 vss ad12 signal name ball number
datasheet 69 package mechanical specifications and pin information vss ad34 vss ad36 vss ad38 vss ad42 vss ae3 vss ae15 vss ae17 vss ae19 vss ae21 vss ae23 vss ae25 vss ae27 vss ae29 vss ae31 vss ae39 vss af6 vss af8 vss af34 vss af42 vss ag3 vss ag15 vss ag17 vss ag19 vss ag21 vss ag23 vss ag25 vss ag27 vss ag29 vss ag31 vss ag39 vss ah6 vss ah8 vss ah10 vss ah12 vss ah34 vss ah36 vss ah38 vss ah42 signal name ball number vss aj3 vss aj15 vss aj17 vss aj19 vss aj21 vss aj23 vss aj25 vss aj27 vss aj29 vss aj31 vss aj39 vss ak6 vss ak8 vss ak34 vss ak42 vss al3 vss al15 vss al17 vss al19 vss al21 vss al23 vss al25 vss al27 vss al29 vss al31 vss al39 vss am6 vss am8 vss am10 vss am12 vss am34 vss am36 vss am38 vss am42 vss an3 vss an15 vss an17 vss an19 signal name ball number
package mechanical specific ations and pi n information 70 datasheet vss an21 vss an23 vss an25 vss an27 vss an29 vss an31 vss an39 vss ap6 vss ap8 vss ap34 vss ap42 vss ar3 vss ar15 vss ar17 vss ar19 vss ar21 vss ar23 vss ar25 vss ar27 vss ar29 vss ar31 vss ar35 vss ar37 vss ar39 vss at6 vss at8 vss at10 vss at12 vss at36 vss at38 vss at42 vss au3 vss au7 vss au9 vss au15 vss au17 vss au19 vss au21 signal name ball number vss au23 vss au25 vss au27 vss au29 vss au31 vss au35 vss au37 vss au39 vss av6 vss av12 vss av34 vss av36 vss av42 vss av44 vss aw1 vss aw3 vss aw9 vss aw11 vss aw13 vss aw15 vss aw17 vss aw19 vss aw21 vss aw23 vss aw25 vss aw27 vss aw29 vss aw31 vss aw33 vss aw35 vss aw37 vss aw39 vss ay6 vss ay12 vss ay34 vss ay42 vss ay44 vss b4 signal name ball number
datasheet 71 package mechanical specifications and pin information vss b6 vss b36 vss b42 vss ba1 vss ba3 vss ba9 vss ba11 vss ba13 vss ba15 vss ba17 vss ba19 vss ba21 vss ba23 vss ba25 vss ba27 vss ba29 vss ba31 vss ba33 vss ba39 vss ba43 vss bb2 vss bb6 vss bb12 vss bb36 vss bb42 vss bc3 vss bc9 vss bc11 vss bc15 vss bc17 vss bc19 vss bc21 vss bc23 vss bc25 vss bc27 vss bc29 vss bc31 vss bc33 signal name ball number vss bc41 vss bd4 vss bd6 vss bd36 vss bd38 vss bd40 vss c3 vss c11 vss c15 vss c17 vss c19 vss c21 vss c23 vss c25 vss c27 vss c29 vss c31 vss c39 vss d2 vss d6 vss d36 vss d42 vss d44 vss e1 vss e3 vss e9 vss e15 vss e17 vss e19 vss e21 vss e23 vss e25 vss e27 vss e29 vss e31 vss e39 vss f6 vss f42 signal name ball number
package mechanical specific ations and pi n information 72 datasheet vss f44 vss g1 vss g3 vss g9 vss g15 vss g17 vss g19 vss g21 vss g23 vss g25 vss g27 vss g29 vss g31 vss g37 vss h6 vss h10 vss h34 vss h38 vss h42 vss j3 vss j15 vss j17 vss j19 vss j21 vss j23 vss j25 vss j27 vss j29 vss j31 vss j39 vss k6 vss k8 vss k34 vss k42 vss l3 vss l15 vss l17 vss l19 signal name ball number vss l21 vss l23 vss l25 vss l27 vss l29 vss l31 vss l39 vss m6 vss m8 vss m10 vss m12 vss m34 vss m36 vss m38 vss m42 vss n3 vss n15 vss n17 vss n19 vss n21 vss n23 vss n25 vss n27 vss n29 vss n31 vss n39 vss p6 vss p8 vss p34 vss p42 vss r3 vss r15 vss r17 vss r19 vss r21 vss r23 vss r25 vss r27 signal name ball number
datasheet 73 package mechanical specifications and pin information vss r29 vss r31 vss r39 vss t6 vss t8 vss t10 vss t12 vss t34 vss t36 vss t38 vss t42 vss u3 vss u5 vss u15 vss u17 vss u19 vss u21 vss u23 vss u25 vss u27 vss u29 vss u31 vss u39 vss v6 vss v8 vss v34 vss v42 vss w3 vss w15 vss w17 vss w19 vss w21 vss w23 vss w25 vss w27 vss w29 vss w31 vss w39 signal name ball number vss y6 vss y8 vss y10 vss y12 vss y34 vss y36 vss y38 vss y42 vsssense bc13 signal name ball number
package mechanical specific ations and pi n information 74 datasheet
datasheet 75 package mechanical specifications and pin information 4.3 alphabetical signals reference table 22. signal description (sheet 1 of 7) name type description a[35:3]# input/ output a[35:3]# (address) define a 2 36 -byte physical memory address space. in sub- phase 1 of the address phase, these pins tr ansmit the address of a transaction. in sub-phase 2, these pins transmit transaction type information. these signals must connect the appropriate pins of both agen ts on the processor fsb. a[35:3]# are source synchronous signals and are latched into the receiving buffers by adstb[1:0]#. address signals are used as straps which are sampled before reset# is deasserted. a20m# input if a20m# (address-20 mask) is asserted, th e processor masks physical address bit 20 (a20#) before looking up a line in any internal cache and before driving a read/ write transaction on the bus. asserting a20m# emulates the 8086 processor's address wrap-around at the 1-mbyte bo undary. assertion of a20m# is only supported in real mode. a20m# is an asynchronous signal. however, to ensure recognit ion of this signal following an input/output write instruction, it must be valid along with the trdy# assertion of the corresponding in put/output write bus transaction. ads# input/ output ads# (address strobe) is asserted to indicate the validity of the transaction address on the a[35:3]# and req[4:0]# pi ns. all bus agents observe the ads# activation to begin parity checking, prot ocol checking, address decode, internal snoop, or deferred reply id match operations associated with the new transaction. adstb[1:0]# input/ output address strobes are used to latch a[35:3]# and req[4:0]# on their rising and falling edges. strobes are associat ed with signals as shown below. bclk[1:0] input the differential pair bclk (bus clock) determines the fsb frequency. all fsb agents must receive these signals to drive their outputs and latch their inputs. all external timing parameters are specif ied with respect to the rising edge of bclk0 crossing v cross . bnr# input/ output bnr# (block next request) is used to as sert a bus stall by any bus agent who is unable to accept new bus transactions. du ring a bus stall, th e current bus owner cannot issue any new transactions. bpm[2:1]# bpm[3,0]# output input/ output bpm[3:0]# (breakpoint monitor) are breakp oint and performance monitor signals. they are outputs from the processor which indicate the status of breakpoints and programmable counters used for monito ring processor performance. bpm[3:0]# should connect the appropriate pins of all processor fsb agents.this includes debug or performance monitoring tools. bpri# input bpri# (bus priority request) is used to ar bitrate for ownership of the fsb. it must connect the appropriate pins of both fsb agents. observing bpri# active (as asserted by the priority agent) causes the other agent to stop issuing new requests, unless such requ ests are part of an ongoing locked operation. the priority agent keeps bpri# asserted until all of its requests are completed, then releases the bus by deasserting bpri#. br0# input/ output br0# is used by the processor to request the bus. the arbitrat ion is done between processor (symmetric agent) and (g)mch (high priority agent). signals associated strobe req[4:0]#, a[16:3]# adstb[0]# a[35:17]# adstb[1]#
package mechanical specific ations and pi n information 76 datasheet bsel[2:0] output bsel[2:0] (bus select) are used to sele ct the processor in put clock frequency. ta b l e 3 defines the possible combinations of the signals and the frequency associated with each combination. the re quired frequency is determined by the processor, chipset and clock synthesizer. all agents must operate at the same frequency. comp[3:0] analog comp[3:0] must be terminated on th e system board us ing precision (1% tolerance) resistors. d[63:0]# input/ output d[63:0]# (data) are the data signals. these signals provide a 64-bit data path between the fsb agents, and must connect the appropriate pins on both agents. the data driver asserts drdy# to indicate a valid data transfer. d[63:0]# are quad-pum ped signals and are driven four times in a common clock period. d[63:0]# are latched off the fa lling edge of both dstbp[3:0]# and dstbn[3:0]#. each group of 16 data signals corresponds to a pair of one dstbp# and one dstbn#. the following table shows the grouping of data signals to data strobes and dinv# . furthermore, the dinv# pins determine the polari ty of the data signals. each group of 16 data signals corresponds to one dinv# signal. when the dinv# signal is active, the corresponding data group is inverted and therefore sampled active high. dbr# output dbr# (data bus reset) is us ed only in processor system s where no debug port is implemented on the system board. dbr# is used by a debug port interposer so that an in-target probe can drive system re set. if a debug port is implemented in the system, dbr# is a no-connect in the system. dbr# is not a processor signal. dbsy# input/ output dbsy# (data bus busy) is asserted by the agent responsible for driving data on the fsb to indicate that the data bus is in use. the data bus is released after dbsy# is deasserted. this si gnal must connect the appr opriate pins on both fsb agents. defer# input defer# is asserted by an agent to in dicate that a transaction cannot be guaranteed in-order completion. assertion of defer# is normally the responsibility of the addressed memory or input/output agent. this signal must connect the appropriate pins of both fsb agents. table 22. signal descript ion (sheet 2 of 7) name type description quad-pumped signal groups data group dstbn#/ dstbp# dinv# d[15:0]# 0 0 d[31:16]# 1 1 d[47:32]# 2 2 d[63:48]# 3 3
datasheet 77 package mechanical specifications and pin information dinv[3:0]# input/ output dinv[3:0]# (data bus inversio n) are source synchronous and indicate the polarity of the d[63:0]# signals. the dinv[3:0]# signals are activated when the data on the data bus is inverted. the bus agent in verts the data bus signals if more than half the bits, within the covered group, would change level in the next cycle. dprstp# input dprstp# when asserted on the platform causes the pr ocessor to transition from the deep sleep state to the deeper sleep state. in order to return to the deep sleep state, dprstp# must be deasserted. dprstp# is driven by the intel 82801hbm ich8m i/o controller hub-based chipset. dpslp# input dpslp# when asserted on th e platform causes the proce ssor to transition from the sleep state to the deep sleep state. in or der to return to the sleep state, dpslp# must be deasserted. dpslp# is driven by the intel 82801hbm ich8m chipset. dpwr# input/ output dpwr# is a control signal used by the ch ipset to reduce power on the processor data bus input buffers. the processor drives this pin during dynamic fsb frequency switching . drdy# input/ output drdy# (data ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. in a multi-common clock data transfer, drdy# may be deasserted to insert idle clocks. this signal must connect the appropriate pins of both fsb agents. dstbn[3:0]# input/ output data strobe used to latch in d[63:0]#. dstbp[3:0]# input/ output data strobe used to latch in d[63:0]#. table 22. signal description (sheet 3 of 7) name type description dinv[3:0]# assignment to data bus bus signal data bus signals dinv[3]# d[63:48]# dinv[2]# d[47:32]# dinv[1]# d[31:16]# dinv[0]# d[15:0]# signals associated strobe d[15:0]#, dinv[0]# dstbn[0]# d[31:16]#, dinv[1]# dstbn[1]# d[47:32]#, dinv[2]# dstbn[2]# d[63:48]#, dinv[3]# dstbn[3]# signals associated strobe d[15:0]#, dinv[0]# dstbp[0]# d[31:16]#, dinv[1]# dstbp[1]# d[47:32]#, dinv[2]# dstbp[2]# d[63:48]#, dinv[3]# dstbp[3]#
package mechanical specific ations and pi n information 78 datasheet ferr#/pbe# output ferr# (floating-point error)/pbe#(pending break event) is a multiplexed signal and its meaning is qualified with stpclk #. when stpclk# is not asserted, ferr#/ pbe# indicates a floating point when the processor detects an unmasked floating- point error. ferr# is similar to the error# signal on the intel 387 coprocessor, and is included for compatibility with sy stems using ms-dos*-type floating-point error reporting. when stpclk # is asserted, an assertio n of ferr#/pbe# indicates that the processor has a pending break even t waiting for service. the assertion of ferr#/pbe# indicates that the processor sh ould be returned to the normal state. when ferr#/pbe# is asserted, indicating a break event, it re mains asserted until stpclk# is deasserted. assertion of preq # when stpclk# is active also causes an ferr# break event. for additional information on the pendin g break event functionality, including identification of support of the feature and enable/disable information, refer to volumes 3a and 3b of the intel? 64 and ia-32 architec tures software developer?s manual and the inte l? processor identification and cpuid instruction application note. gtlref input gtlref determines the signal reference level for agtl+ input pins. gtlref should be set at 2/3 v ccp . gtlref is used by the agtl+ receivers to determine if a signal is a logical 0 or logical 1. hit# hitm# input/ output input/ output hit# (snoop hit) and hitm# (hit modified) convey transaction snoop operation results. either fsb agent ma y assert both hit# and hitm# together to indicate that it requires a snoop st all, which can be continue d by reasserting hit# and hitm# together. ierr# output ierr# (internal error) is asserted by a proc essor as the result of an internal error. assertion of ierr# is usually accompanied by a shutdown transaction on the fsb. this transaction may optionally be conv erted to an external error signal (e.g., nmi) by system core logic. the processor keeps ierr# asserted until the assertion of reset#, binit#, or init#. ignne# input ignne# (ignore numeric error) is asserted to force th e processor to ignore a numeric error and continue to execute nonc ontrol floating-point instructions. if ignne# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point in struction caused an error. ignne# has no effect when the ne bit in control register 0 (cr0) is set. ignne# is an asynchronous signal. however, to ensure recognition of this signal following an input/output wr ite instruction, it must be valid along with the trdy# assertion of the corresponding in put/output write bus transaction. init# input init# (initialization), when asserted, resets in teger registers inside the processor without affecting its internal caches or floating-point re gisters. the processor then begins execution at the power-on rese t vector configured during power-on configuration. the processor continues to handle snoop requests during init# assertion. init# is an asynchronous signal . however, to ensure recognition of this signal following an input/output write inst ruction, it mu st be valid along with the trdy# assertion of the corresponding inpu t/output write bus transaction. init# must connect the appropriate pins of both fsb agents. if init# is sampled active on the active to inactive transition of reset#, then the processor executes its built-in self-test (bist) table 22. signal descript ion (sheet 4 of 7) name type description
datasheet 79 package mechanical specifications and pin information lint[1:0] input lint[1:0] (local apic interrupt) must conne ct the appropriate pi ns of all apic bus agents. when the apic is disabled, the lint0 signal becomes intr, a maskable interrupt request signal, and lint1 beco mes nmi, a nonmaskable interrupt. intr and nmi are backward compatible with th e signals of those names on the intel? pentium? processor. both signals are asynchronous. both of these signals must be software configured via bios programming of the apic register space to be used either as nmi/intr or lint[1:0]. because the apic is enabled by default after reset, operation of these pins as lint[1:0] is the default configuration. lock# input/ output lock# indicates to the system that a transa ction must occur atomically. this signal must connect the appropriate pins of both fsb agents. for a locked sequence of transactions, lock# is assert ed from the beginning of the first transaction to the end of the last transaction. when the priority agent asserts bpri# to arbitrate for ownership of the fsb, it waits until it observes lock# deasserted. this enables symmetric agents to retain ownership of the fsb throughout the bus locked operation and ensure the atomicity of lock. prdy# output probe ready signal used by debug tools to determine proc essor debug readiness. preq# input probe request signal used by debug t ools to request debug operation of the processor. prochot# input/ output as an output, prochot# (processor ho t) goes active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. this indicates that the processor thermal control circuit (tcc) has been activated, if enabled. as an input, assertion of prochot# by the system activates the t cc, if enabled. the tcc remains active until the system deasserts prochot#. by default prochot# is configured as an output. the processor must be enabled via the bios for prochot# to be configured as bidirectional. this signal may require voltage translation on the motherboard. psi# output processor power status indicator signal. this signal is asserted when the processor is in both in the normal state (hfm to lfm) and in lower powe r states (deep sleep and deeper sleep). pwrgood input pwrgood (power good) is a processor input. the processor requir es this signal to be a clean indication that the clocks and powe r supplies are stable and within their specifications. ?clean? implies that the signal remains low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specific ation. the signal mu st then transition monotonically to a high state. pwrgood ca n be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of pwrgood. the pwrgood signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. it should be driven high throughout boundary scan operation. req[4:0]# input/ output req[4:0]# (request command) must conn ect the appropriate pins of both fsb agents. they are asserted by the current bus owner to de fine the currently active transaction type. these signals are source synchronous to adstb[0]#. table 22. signal description (sheet 5 of 7) name type description
package mechanical specific ations and pi n information 80 datasheet reset# input asserting the reset# signal resets the pr ocessor to a known state and invalidates its internal caches without writing back any of their contents. for a power-on reset, reset# must stay active for at least two milliseconds after v cc and bclk have reached their proper specifications . on observing active reset#, both fsb agents deasserts their outputs within two clocks. all processor straps must be valid within the specified setup time before reset# is deasse rted. there is a 55- (nominal) on die pull-up re sistor on this signal. rs[2:0]# input rs[2:0]# (response status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of both fsb agents. rsvd reserved /no connect these pins are reserved and must be left unconnected on the board. however, it is recommended that routing channels to these pins on the board be kept open for possible future use. slp# input slp# (sleep), when asserted in stop-grant state, caus es the processor to enter the sleep state. during sleep state, the processor stops providing internal clock signals to all units, leaving only the ph ase-locked loop (pll) still operating. processors in this state does not recognize snoops or interrupts. the processor recognizes only assertion of the reset# signal, deassertion of slp#, and removal of the bclk input while in sleep state. if slp# is deasserted , the processor exits sleep state and returns to stop-grant state, restarting its internal clock signals to the bus and processor core units. if dpslp# is asserted while in the sleep state, the processor exits the sleep state and transition to the deep sleep state. smi# input smi# (system management interrupt) is asse rted asynchronously by system logic. on accepting a system management inte rrupt, the processor saves the current state and enters system management mode (smm). an smi acknowledge transaction is issued and the processo r begins program execution from the smm handler. if an smi# is asserted during the de assertion of reset#, then the processor tristates its outputs. stpclk# input stpclk# (stop clock), when asserted, caus es the processor to enter a low power stop-grant state. the processor issues a stop-grant acknowledge transaction, and stops providing internal clock signals to all processor core units except the fsb and apic units. the processor continues to snoop bus transactions and service interrupts while in stop-grant state. wh en stpclk# is deasse rted, the processor restarts its internal clock to all units and resume s execution. the assertion of stpclk# has no effect on the bus cloc k; stpclk# is an asynchronous input. tck input tck (test clock) provides the clock input for the processor test bus (also known as the test access port). tdi input tdi (test data in) transfers serial test data into the processor. tdi provides the serial input needed for jtag specification support. tdo output tdo (test data out) transfers serial test data out of the processor. tdo provides the serial output needed for jtag specification support. test1, test2, test3, test4, test5, test6 input test1 and test2 must have a stuffing opti on of separate pulldown resistors to v ss . for the purpose of testability, rout e the test3 and test5 signals through a ground-referenced zo=55 trace that ends in a via th at is near a gnd via and is accessible through an oscilloscope connection. thrmda other thermal diode anode. thrmdc other thermal diode cathode. table 22. signal descript ion (sheet 6 of 7) name type description
datasheet 81 package mechanical specifications and pin information thermtrip# output the processor protects itself from catastrophic overhe ating by use of an internal thermal sensor. this sensor is set well above the normal operating temperature to ensure that there are no false trips. the processor stops all execution when the junction temperature exceeds approximately 125 c. this is signalled to the system by the thermtrip# (thermal trip) pin. tms input tms (test mode select) is a jtag spec ification support signal used by debug tools. trdy# input trdy# (target ready) is asserted by the ta rget to indicate that it is ready to receive a write or implicit writeback data transfer. trdy# must connect the appropriate pins of both fsb agents. trst# input trst# (test reset) resets the test access port (tap) logic. tr st# must be driven low during power on reset. v cc input processor core power supply. v ss input processor core ground node. v cca input v cca provides isolated power for th e internal processor core pll?s . v ccp input processor i/o power supply. v cc_sense output v cc_sense together with v ss_sense are voltage feedback signals to intel? mvp-6 that control the 2.1-m loadline at the processor die. it should be used to sense voltage near the silicon with little noise. vid[6:0] output vid[6:0] (voltage id) pins are used to support automatic sele ction of power supply voltages (v cc ). unlike some previous generations of processors, these are cmos signals that are driven by the processor. the voltage su pply for these pins must be valid before the vr can supply vcc to th e processor. conversely, the vr output must be disabled until th e voltage supply for the vid pins becomes valid. the vid pins are needed to support the processo r voltage specification variations. see ta b l e 2 for definitions of these pins. the vr must supply the voltage that is requested by the pins , or disable itself. v ss_sense output v ss_sense together with v cc_sense are voltage feedback signals to intel mvp-6 that control the 2.1-m loadline at the processor die. it should be used to sense ground near the silicon with little noise. table 22. signal description (sheet 7 of 7) name type description
package mechanical specific ations and pi n information 82 datasheet
datasheet 83 thermal specifications and design considerations 5 thermal specifications and design considerations maintaining the proper thermal environmen t is key to reliable, long-term system operation. a complete thermal solution in cludes both component and system level thermal management features. the system/processor thermal solution should be designed so that the processor remains within the minimum and maximum junction temperature (tj) specifications at the corre sponding thermal design power (tdp) value listed in ta b l e 2 4 through ta b l e 2 6 . caution: operating the processor outside these limits may result in permanent damage to the processor and potentially other components in the system. notes: 1. the tdp specification should be used to design the processor thermal solution. the tdp is not the maximum theoretical power the processor can generate. 2. not 100% tested. these power specifications are dete rmined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. table 23. power specifications for the 3x00 celeron processors symbol processor number core frequency & voltage thermal design power unit notes tdp t1600 1.66 ghz 35 w 1, 4, 5, 6, 9 tdp t1700 1.83 ghz 35 w 1, 4, 5, 6, 9 symbol parameter min typ max unit p ah, p sgnt auto halt, stop grant power at hfm v cc 13.9 w 2, 5, 7 p slp sleep power at v cc 13.1 w 2, 5, 7 p dslp deep sleep power at v cc 5.5 w 2, 5, 8 t j junction temperature 0 105 c3, 4 table 24. power specifications for the inte l celeron dual-core processor - standard voltage symbol processor number core frequency & voltage thermal design power unit notes tdp t1600 1.66 ghz 35 w 1, 4, 5, 6, 9 tdp t1700 1.83 ghz 35 w 1, 4, 5, 6, 9 symbol parameter min typ max unit p ah, p sgnt auto halt, stop grant power at hfm v cc 13.5 w 2, 5, 7 p slp sleep power at v cc 12.9 w 2, 5, 7 p dslp deep sleep power at v cc 7.7 w 2, 5, 8 t j junction temperature 0 100 c3, 4
thermal specifications and design considerations 84 datasheet 3. as measured by the activation of the on-die intel thermal monitor. the intel thermal monitor?s automatic mode is used to indicate that the maximum t j has been reached. refer to section 5.1 for details. 4. the intel thermal monitor automatic mode must be enabled for the processor to operate within specifications. 5. at tj of 100 o c 6. at tj of 50 o c 7. at tj of 35 o c 8. 512-kb l2 cache table 25. power specifications for the ul tra low voltage dual-core 1m cache intel celeron (sff) genuine intel processor notes: 1. the tdp specification should be used to design the processor thermal solution. the tdp is not the maximum theoretical power th e processor can generate. 2. not 100% tested. these power specifications are dete rmined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. as measured by the activation of the on-die intel thermal monitor. the intel thermal monitor?s automatic mode is used to indicate that the maximum t j has been reached. refer to section 5.1 for more details. 4. the intel thermal monitor automatic mode must be enabled for the processor to operate within specifications. 5. at tj of 100 o c 6. at tj of 50 c 7. at tj of 35 o c 5.1 monitoring die temperature the processor incorporates three methods of monitoring die temperature: ?thermal diode ? intel thermal monitor ? digital thermal sensor symbol processor number core frequency thermal design power unit notes tdp su2300 1.2 ghz 10 w 1, 4, 5 symbol parameter min typ max unit notes p ah, p sgnt auto halt, stop grant power 2.9 w 2, 6 p slp sleep power 2.9 w 2, 6 p dslp deep sleep power 1.3 w 2,7 p dprslp deeper sleep power 0.6 w 2, 7 t j junction temperature 0 100 c3,4
datasheet 85 thermal specifications and design considerations 5.1.1 thermal diode the processor incorporates an on-die pnp transistor whose base emitter junction is used as a thermal diode, with its collector shorted to ground. the thermal diode can be read by an off-die analog/digital converter (a thermal sensor) located on the motherboard or a stand-alone measurement kit. the thermal diode may be used to monitor the die temperature of the processor for thermal management or instrumentation purposes but is not a relia ble indication that the maximum operating temperature of the processor has been reached. when using the thermal diode, a temperature offset value must be read from a processor msr and applied. see section 5.1.2 for more details. please see section 5.1.3 for thermal diode usage recommendation when the prochot# signal is not asserted. the reading of the extern al thermal sensor (on the motherboard) connected to the processor thermal diode signals do es not reflect the temperature of the hottest location on the die. this is due to inaccuracies in the external thermal sensor, on-die temperature gradients between the location of the thermal diode and the hottest location on the die, and time based variations in the die temperature measurement. time-based variations can occur when the sampling rate of the thermal diode (by the thermal sensor) is slow er than the rate at which the t j temperature can change. offset between the thermal diode-based temperature reading and the intel thermal monitor reading may be characterized using the intel thermal monitor?s automatic mode activation of the thermal control circui t. this temperature offset must be taken into account when using the processor thermal diode to implement power management events. this offset is different than the diode toffset value programmed into the processor model specific register (msr). ta b l e 2 6 to ta b l e 2 9 provide the diode interface and specifications. the diode model parameters apply to the traditional therma l sensors that use the diode equation to determine the processor temperature. transistor model parameters have been added to support thermal sensors that use the transistor equation method. the transistor model may provide more accurate temperature measurements when the diode ideality factor is closer to the maximum or minimum limits. contact your external sensor supplier for recommendations. the thermal di ode is separate from the intel thermal monitor?s thermal sensor and cannot be used to predict the behavior of the intel thermal monitor. table 26. thermal diode interface signal name pin/ball number signal description thermda a24 thermal diode anode thermdc a25 thermal diode cathode
thermal specifications and design considerations 86 datasheet notes: 1. intel does not support or re commend operation of the thermal diode under reverse bias. intel does not support or recommend operation of the thermal diode when the processor power supplies are not within th eir specified tolerance range. 2. characterized across a temperature range of 50-100c. 3. not 100% tested. specified by design characterization. 4. the ideality factor, n, represents the deviat ion from ideal diode behavior as exemplified by the diode equation: i fw = i s * (e qv d /nkt ?1) where i s = saturation current, q = electronic charge, v d = voltage across the diode, k = boltzmann constant, and t = absolute temperature (kelvin). 5. the series resistance, r t , is provided to allow for a mo re accurate measurement of the junction temperature. r t , as defined, includes the land s of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor. r t can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term. another application is that a temperat ure offset can be manually calculated and programmed into an offset register in the remote diode ther mal sensors as exemplified by the equation: t error = [r t * (n-1) * i fwmin ] / [nk/q * ln n] where t error = sensor temperature error, n = se nsor current ratio, k = boltzmann constant, q = electronic charge. table 27. thermal diode parameters using diode model symbol parameter min typ max unit notes i fw forward bias current 5 200 a 1 n diode ideality factor 1.000 1.009 1.050 2, 3, 4 r t series resistance 2.79 4.52 6.24 2, 3, 5
datasheet 87 thermal specifications and design considerations notes: 1. intel does not support or recommend operation of the thermal diode under reverse bias. 2. same as i fw in ta b l e 2 7 . 3. characterized acro ss a temperature range of 50-100c. 4. not 100% tested. specified by design characterization. 5. the ideality factor, nq, represents the devi ation from ideal transistor model behavior as exemplified by the equation for the collector current: i c = i s * (e qv be /n q kt ?1) where i s = saturation current, q = electronic charge, v be = voltage across the transistor base emitter junction (same nodes as vd), k = boltzmann constant, and t = absolute temperature (kelvin). 6. the series resistance, r t , provided in the diode model table ( ta b l e 2 7 ) can be used for more accurate readings as needed. when calculating a temperature based on the thermal diode measurements, a number of parameters must be either measured or assumed. most devices measure the diode ideality and assume a series resistance and ideality trim value, although are capable of also measuring the series resistance. calculating the temperature is then accomplished using the equations listed under ta b l e 2 7 . in most sensing devices, an expected value for the diode ideality is designed-in to the temperature calculation equation. if the designer of the temperature sensing device assumes a perfect diode, the ideality value (also called n trim ) is 1.000. given that most diodes are not perfect, the designers usually select an n trim value that more closely matches the behavior of the diodes in the processor. if the processor diode ideality deviates from that of the n trim , each calculated temperature offsets by a fixed amount. this temperature offset can be calculated with the equation: t error(nf) = t measured * (1 - n actual /n trim ) where t error(nf) is the offset in degrees c, t measured is in kelvin, n actual is the measured ideality of the diode, and n trim is the diode ideality assumed by the temperature sensing device. 5.1.2 thermal diode offset in order to improve the accuracy of the diode-based temperature measurements, a temperature offset value (specified as to ffset) is programmed in the processor msr which contains thermal diode characterization data. during manufacturing each processor thermal diode is evaluated for its behavior relative to the theoretical diode. using the equation above, the temperat ure error created by the difference n trim and the actual ideality of the particular processor is calculated. table 28. thermal diode parame ters using transistor model symbol parameter min typ max unit notes i fw forward bias current 5 200 a1,2 i e emitter current 5 200 a1 n q transistor ideality 0.997 1.001 1.005 3,4,5 beta 0.3 0.760 3,4 r t series resistance 2.79 4.52 6.24 3,6
thermal specifications and design considerations 88 datasheet if the n trim value used to calculate the toffset differs from the n trim value used to in a temperature sensing device, the t error(nf) may not be accurate. if desired, the toffset can be adjusted by calculating n actual and then recalculating the offset using the n trim as defined in the temperature sensor manufacturer?s datasheet. the n trim used to calculate the diode correction toffset are listed in ta b l e 2 9 . 5.1.3 intel? thermal monitor the intel thermal monitor helps control the processor temperature by activating the tcc (thermal control circuit) when th e processor silicon reaches its maximum operating temperature. the temperature at which the intel thermal monitor activates the tcc is not user configurable. bus traffic is snooped in the normal manner and interrupt requests are latched (and serviced during the time that the clocks are on) while the tcc is active. with a properly designed and characterized thermal solution, it is anticipated that the tcc would only be activated for very shor t periods of time when running the most power intensive applications. the processo r performance impact due to these brief periods of tcc activation is expected to be minor and hence not detectable. an under- designed thermal solution that is not able to prevent excessive activation of the tcc in the anticipated ambient environment may cause a noticeable performance loss and may affect the long-term reliability of the proc essor. in addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the tcc is active continuously. the intel thermal monitor controls the processor temperature by modulating (starting and stopping) the processor core clocks when the processor silicon reaches its maximum operating temperature. the intel thermal monitor uses two modes to activate the tcc: automatic mode and on-demand mode. if both modes are activated, automatic mode takes precedence. there are two automatic modes called intel thermal monitor 1 and intel thermal monitor 2. these modes are selected by writing values to the msrs of the processor. after automatic mode is enabled, the tc c activates only when the internal die temperature reaches the maximum allowed value for operation. when intel thermal monitor 1 is enabled an d a high temperature situation exists, the clocks modulates by alternately turning the clocks off and on at a 50% duty cycle. cycle times are processor speed dependent and decreases linearly as processor core frequencies increase. once the temperature has returned to a non-critical level, modulation ceases and tcc goes inactive. a small amount of hysteresis has been included to prevent rapid active/inactive transitions of the tcc when the processor temperature is near the trip point. the duty cycle is factory configured and cannot be modified. also, automatic mode does not require any additional hardware, software drivers, or interrupt handling routines. pr ocessor performance decreases by the same amount as the duty cycle when the tcc is active. note: intel thermal monitor 1 and intel thermal monitor 2 features are collectively referred to as adaptive thermal monitoring features. intel recommends intel thermal monitor 1 and 2 be enabled on the processors. table 29. thermal diode n trim and diode correction toffset symbol parameter value n trim diode ideality used to calculate toffset 1.01
datasheet 89 thermal specifications and design considerations intel thermal monitor 1 and 2 can co-exist wi thin the processor. if both intel thermal monitor 1 and 2 bits are enabled in the auto-throttle msr, intel thermal monitor 2 takes precedence over intel thermal monitor 1. however, if force intel thermal monitor 1 over intel thermal monitor 2 is enabled in msrs via bios and intel thermal monitor 2 is not sufficient to cool the processor below the maximum operating temperature, then intel thermal monitor 1 also activates to help cool down the processor. the tcc may also be activated via on-demand mode. if bit 4 of the acpi intel thermal monitor control register is written to a 1, the tcc activates immediately independent of the processor temperature. when using on-demand mode to activate the tcc, the duty cycle of the clock modulation is programmable via bits 3:1 of the same acpi intel thermal monitor control register. in automati c mode, the duty cycle is fixed at 50% on, 50% off, however in on-demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. on-demand mode may be used at the same time automatic mode is enabled, however, if the system tries to enable the tcc via on-demand mode at the same time automatic mode is enabled and a high temperature condition exists, automatic mode takes precedence. an external signal, prochot# (processor hot) is asserted when the processor detects that its temperature is above the therma l trip point. bus snooping and interrupt latching are also active while the tcc is active. besides the thermal sensor and thermal control circuit, the intel thermal monitor also includes one acpi register, one performanc e counter register, three msr, and one i/o pin (prochot#). all are available to monitor and control the state of the intel thermal monitor feature. the intel thermal monitor can be configured to generate an interrupt upon the assertion or deassertion of prochot#. prochot# is not be asserted when the processor is in the stop grant, sleep, deep sleep, and deeper sleep low power states, hence the thermal diode reading must be used as a safeguard to maintain the proc essor junction temperature within maximum specification. if the platform thermal soluti on is not able to maintain the processor junction temperature within the maximum spec ification, the system must initiate an orderly shutdown to prevent damage. if the processor enters one of the above low power states with prochot# already asserted, prochot# will remain asserted until the processor exits the low power state and the processor junction temperature drops below the thermal trip point. if intel thermal monitor automatic mode is disabled, the processor will be operating out of specification. regardless of enabling th e automatic or on-demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 125c. at this point the thermtrip# signal will go active. thermtri p# activation is independent of processor activity and does not generate any bus cycles. when thermtrip# is asserted, the processor core voltage must be shut down within the time specified in chapter 3 . in all cases, the intel thermal monitor feat ure must be enabled for the processor to remain within specification. 5.1.4 digital thermal sensor the processor also contains an on die digital thermal sensor (dts) that can be read via an msr (no i/o interface). each core of the processor will have a unique digital thermal sensor whose temperature is accessible via the processor msrs. the dts is the preferred method of reading the processor die temperature since it can be located much closer to the hottest portions of the die and can thus more accurately track the die temperature and potential activation of processor core clock modulation via the intel thermal monitor. the dts is only valid while the processor is in the normal operating state (the normal package level low-power state).
thermal specifications and design considerations 90 datasheet unlike traditional thermal devices, the dts will output a temperature relative to the maximum supported operating temperature of the processor (t j,max ). it is the responsibility of software to convert th e relative temperature to an absolute temperature. the temperature returned by the dts will always be at or below t j,max . catastrophic temperature conditions are detectable via an out of spec status bit. this bit is also part of the dts msr. when this bit is set, the processor is operating out of specification and immediate shutdown of the system should occur. the processor operation and code execution is not guaranteed once the activation of the out of spec status bit is set. the dts-relative temperature readout corresp onds to the intel thermal monitor 1/intel thermal monitor 2 trigger point. when the dts indicates maximum processor core temperature has been reached, the intel thermal monitor 1 or 2 hardware thermal control mechanism will activate. the dts and intel thermal monitor 1/intel thermal monitor 2 temperature may not correspond to the thermal diode reading because the thermal diode is located in a separate portion of the die and thermal gradient between the individual core dts. additionally, the thermal gradient from dts to thermal diode can vary substantially due to changes in processor power, mechanical and thermal attach, and software application. the system designer is required to use the dts to guarantee proper operation of the proc essor within its temperature operating specifications. changes to the temperature can be detected via two programmable thresholds located in the processor msrs. these thresholds ha ve the capability of generating interrupts via the core's local apic. refer to the intel? 64 and ia-32 architectures software developer?s manual for specific register and programming details. 5.1.5 out of specification detection overheat detection is performed by monitoring the processor temperature and temperature gradient. this feature is intended for graceful shut down before the thermtrip# is activated. if the processor? s intel thermal monitor 1 or 2 are triggered and the temperature remains high, an ?out of spec? status and sticky bit are latched in the status msr register and generates thermal interrupt. 5.1.6 prochot# signal pin an external signal, prochot# (processor hot), is asserted when the processor die temperature has reached its maximum operatin g temperature. if intel thermal monitor 1 or 2 is enabled, then the tcc will be active when prochot# is asserted. the processor can be configured to generate an interrupt upon the assertion or deassertion of prochot#. refer to the intel? 64 and ia-32 architectures software developer?s manual for specific register and programming details. the processor implements a bi-directional prochot# capability to allow system designs to protect various components from overheating situations. the prochot# signal is bi-directional in that it can either signal when the processor has reached its maximum operating temperature or be driven from an external source to activate the tcc. the ability to activate the tcc via prochot# can provide a means for thermal protection of system components. only a single prochot# pin exists at a pa ckage level of the processor. when either core's thermal sensor trips, the prochot# signal will be driven by the processor package. if only intel thermal monitor 1 is enabled, prochot# will be asserted and only the core that is above tcc temperature trip point will have its core clocks modulated. if intel thermal monitor 2 is enabled, then regardless of which core(s) are above tcc temperature trip point, both core s will enter the lowest programmed intel thermal monitor 2 performance state. it is important to note that intel recommends both intel thermal monitor 1 and 2 to be enabled.
datasheet 91 thermal specifications and design considerations when prochot# is driven by an external agent, if only intel thermal monitor 1 is enabled on both cores, then both processor cores will have their core clocks modulated. if intel thermal monitor 2 is enabled on bo th cores, then both processor cores will enter the lowest programmed intel thermal mo nitor 2 performance state. it should be noted that force intel thermal monitor 1 on intel thermal monitor 2, enabled via bios, does not have any effect on external prochot#. if prochot# is driven by an external agent when intel thermal monitor 1, intel thermal monitor 2, and force intel thermal monitor 1 on intel thermal monitor 2 are all enabled, then the processor will still apply only intel thermal monitor 2. prochot# may be used for thermal protection of voltage regulators (vr). system designers can create a circuit to monitor the vr temperature and activate the tcc when the temperature limit of the vr is re ached. by asserting prochot# (pulled-low) and activating the tcc, the vr will cool do wn as a result of reduced processor power consumption. bi-directional prochot# can allow vr thermal designs to target maximum sustained current instead of maxi mum current. systems should still provide proper cooling for the vr and rely on bi-direc tional prochot# only as a backup in case of system cooling failure. the system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its tdp. with a properly designed and characterized thermal solution, it is anticipated that bi-directional prochot# woul d only be asserted for very short periods of time when running the most power in tensive applications. an under-designed thermal solution that is not able to prevent excessive assertion of prochot# in the anticipated ambient environment may cause a noticeable performance loss.
thermal specifications and design considerations 92 datasheet
datasheet 1 1 coordination of core-level low-power states at the package level................................. 11 2 voltage identification definition ....................... ......................................................... 19 3 bsel[2:0] encoding for bclk frequency ..................................................................... 23 4 fsb pin groups........................................................................................................ 24 5 processor absolute maximum ratings ......................................................................... 25 6 dc voltage and current specifications for the t3x00 celeron processors ......................... 27 7 dc voltage and current specifications for the t1x00 celeron mobile processors................ 28 8 voltage and current specifications for the ultra low voltage dual-core 1m cache intel celeron sff genuine intel processor........................................................................... 29 9 fsb differential bclk specifications .................. ......................................................... 30 10 agtl+ signal group dc specifications ........................................................................ 31 11 cmos signal group dc specifications ......................................................................... 32 12 open drain signal group dc specifications.......... ........................................................ 32 13 the coordinates of the processor pins as viewed from the top of the package (sheet 1 of 2).......................................................................................................... 39 14 the coordinates of the processor pins as viewed from the top of the package (sheet 2 of 2) .......................................................................................................................... 40 15 sff processor top view upper left side ...................................................................... 41 16 sff processor top view upper right side .................................................................... 42 17 sff processor top view lower left side ...................................................................... 43 18 sff processor top view lower right side .................................................................... 44 19 pin listing by pin name............................................................................................. 45 20 pin listing by pin number.......................................................................................... 52 21 sff listing by ball name........................................................................................... 61 22 signal description .................................................................................................... 75 23 power specifications for the 3x00 celeron processors.................................................... 83 24 power specifications for the intel celeron dual -core processor - standard voltage............ 83 25 power specifications for the ultra low vo ltage dual-core 1m cache intel celeron (sff) genuine intel processor ............................................................................................ 84 26 thermal diode interface ........................................................................................... 85 27 thermal diode parameters using diode model.............................................................. 86 28 thermal diode parameters using transistor model.... .................................................... 87 29 thermal diode ntrim and diode correction toffset .... .................................................... 88
2 datasheet
datasheet 1 1 package-level low-power states ............................................................................... 11 2 core low-power states ............................................................................................. 12 3 4-mb and fused 2-mb micro-fcpga processor package drawing (sheet 1 of 2) ................ 34 4 4-mb and fused 2-mb micro-fcpga processor package drawing (sheet 2 of 2) ................ 35 5 2-mb micro-fcpga processor package drawing (sheet 1 of 2)........................................ 36 6 2-mb micro-fcpga processor package drawing (sheet 2 of 2)........................................ 37 7 sff (ulv dc) die micro-fcbga processor package drawing........................................... 38
2 datasheet
datasheet 1 1introduction .............................................................................................................. 7 1.1 terminology ....................................................................................................... 8 1.2 references ......................................................................................................... 9 2 low power features ................................................................................................ 11 2.1 clock control and low power states .................................................................... 11 2.1.1 core low-power states ........................................................................... 12 2.1.1.1 c0 state .................................................................................. 12 2.1.1.2 c1/autohalt powerdown state .................................................. 12 2.1.1.3 c1/mwait powerdown state ...................................................... 13 2.1.1.4 core c2 state........................................................................... 13 2.1.1.5 core c3 state........................................................................... 13 2.1.1.6 core c4 state........................................................................... 13 2.1.2 package low-power states ...................................................................... 13 2.1.2.1 normal state............................................................................ 13 2.1.2.2 stop-grant state ...................................................................... 13 2.1.2.3 stop grant snoop state ............................................................. 14 2.1.2.4 sleep state .............................................................................. 14 2.1.2.5 deep sleep state ...................................................................... 15 2.1.2.6 deeper sleep state ................................................................... 15 2.2 enhanced intel speedstep? technology .............................................................. 15 2.3 low-power fsb features .................................................................................... 16 2.4 processor power status indicator (psi#) signal..................................................... 17 3 electrical specifications ........................................................................................... 19 3.1 power and ground pins ...................................................................................... 19 3.2 fsb clock (bclk[1:0]) and processor clocking ...................................................... 19 3.3 voltage identification ......................................................................................... 19 3.4 catastrophic thermal protection .......................................................................... 22 3.5 reserved and unused pins.................................................................................. 22 3.6 fsb frequency select signals (bsel[2:0])............................................................ 23 3.7 fsb signal groups............................................................................................. 23 3.8 cmos signals ................................................................................................... 25 3.9 maximum ratings.............................................................................................. 25 3.10 processor dc specifications ................................................................................ 26 4 package mechanical specific ations and pin information .......................................... 33 4.1 package mechanical specifications ................ ....................................................... 33 4.2 processor pinout and pin list .............................................................................. 39 4.3 alphabetical signals reference ............................................................................ 75 5 thermal specifications and design considerations .................................................. 83 5.1 monitoring die temperature ............................................................................... 84 5.1.1 thermal diode ....................................................................................... 85 5.1.2 thermal diode offset .............................................................................. 87 5.1.3 intel? thermal monitor........................................................................... 88 5.1.4 digital thermal sensor............................................................................ 89 5.1.5 out of specification detection .................................................................. 90 5.1.6 prochot# signal pin ............................................................................. 90
2 datasheet

▲Up To Search▲

Price & Availability of AC82GL40-SLB95

	To Download AC82GL40-SLB95 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .